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_______________________________________________________________ maxim integrated products 1 for pricing, delivery, and ordering information, please contact maxim direct at 1-888-629-4642, or visit maxims website at www.maxim-ic.com. dual serial uart with 128-word fifos 19-5806; rev 1; 5/12 general description the max3109 advanced dual universal asynchronous receiver-transmitter (uart) has 128 words of receive and transmit first-in/first-out (fifo) and a high-speed spi or i 2 c controller interface. the 2x and 4x rate modes allow a maximum of 24mbps data rates. a phase-locked loop (pll) and the fractional baud-rate generators allow a high degree of flexibility in baud-rate programming and reference clock selection. independent logic-level translation on the transceiver and controller interfaces allows ease of interfacing to microcontrollers, fpgas, and transceivers that are pow - ered by differing supply voltages. automatic hardware and software flow control with selectable fifo interrupt triggering offloads low-level activity from the host control - ler. automatic half-duplex transceiver control with pro - grammable setup and hold times allow the max3109 to be used in high-speed applications such as profibus- dp. the 128-word fifos have advanced fifo control, reducing host processor data flow management. the max3109 is available in a 32-pin tqfn (5mm x 5mm) package and is specified over the -40 c to +85 c extended temperature range. applications features s 24mbps (max) baud rate s integrated pll and divider s 1.71v to 3.6v supply range s high-resolution programmable baud rate s spi up to 26mhz clock rate s fast mode plus i 2 c up to 1mhz s automatic rts_ and cts_ flow control s automatic xon/xoff software flow control s special character detection s 9-bit multidrop mode data filtering s sir- and mir-compliant irda sm encoder/decoder s flexible logic levels on the controller and transceiver interfaces s line noise indication s 1 f a shutdown current s two timers routed to gpios s 8 flexible gpios with 20ma drive capability s register compatible with max3107, max3108, max14830 s small tqfn (5mm x 5mm) package ordering information + denotes a lead(pb)-free/rohs-compliant package. *ep = exposed pad. irda is a service mark of infrared data association corporation. functional diagram handheld devices power meters programmable logic controllers (plcs) medical systems automotive infotainment systems point-of-sales systems hvac or building control max3109 logic-level translation spi and i 2 c interface ldo pll logic-level translation registers and control fractional baud-rate generator uart1 crystal oscillator v 18 v cc dgnd agnd v ext v l ldoen spi/i2c mosi/a1 miso/sda cs/a0 sclk/scl rst irq xin xout gpio4 gpio5 gpio6 gpio7 tx1 rx1 cts1 rts1 divider uart0 gpio0 gpio1 gpio2 gpio3 tx0 rx0 cts0 rts0 2 transmitter sync 2 part temp range pin-package max3109etj+ -40 n c to +85 n c 32 tqfn-ep* max3109
2 ______________________________________________________________________________________ dual serial uart with 128-word fifos absolute maximum ratings ...................................................................... 7 package thermal characteristics .................................................................. 7 dc electrical characteristics ..................................................................... 7 ac electrical characteristics .................................................................... 10 timing diagrams ............................................................................. 12 typical operating characteristics ................................................................ 13 pin configuration ............................................................................. 14 pin description ............................................................................... 14 detailed description ........................................................................... 16 receive and transmit fifos ................................................................... 16 transmitter operation ........................................................................ 17 receiver operation .......................................................................... 17 line noise indication ......................................................................... 18 clock selection ............................................................................. 19 crystal oscillator ......................................................................... 19 external clock source ..................................................................... 19 pll and predivider .......................................................................... 19 fractional baud-rate generators ............................................................... 19 2x and 4x rate modes ....................................................................... 20 low-frequency timer ........................................................................ 20 uart clock to gpio ......................................................................... 21 multidrop mode ............................................................................. 21 auto data filtering in multidrop mode ........................................................... 21 auto transceiver direction control .............................................................. 21 transmitter triggering and synchronization ....................................................... 21 transmitter synchronization ................................................................. 22 intrachip and interchip synchronization ........................................................ 22 delayed triggering ........................................................................ 22 trigger accuracy ......................................................................... 22 synchronization accuracy .................................................................. 23 auto transmitter disable ................................................................... 24 echo suppression ........................................................................... 24 auto hardware flow control ................................................................... 24 autorts control .......................................................................... 24 autocts control .......................................................................... 25 auto software (xon/xoff) flow control ......................................................... 25 receiver flow control ..................................................................... 25 transmitter flow control .................................................................... 26 table of contents max3109
_______________________________________________________________________________________ 3 dual serial uart with 128-word fifos fifo interrupt triggering ...................................................................... 26 low-power standby modes ................................................................... 26 forced-sleep mode ....................................................................... 26 auto-sleep mode ......................................................................... 26 multiple uarts in sleep mode .............................................................. 26 shutdown mode .......................................................................... 27 power-up and irq .......................................................................... 27 interrupt structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 interrupt enabling ......................................................................... 27 interrupt clearing ......................................................................... 27 register map ................................................................................ 28 detailed register descriptions ................................................................... 29 serial controller interface ....................................................................... 57 spi interface ............................................................................... 57 spi single-cycle access ................................................................... 57 spi burst access ......................................................................... 58 fast read cycle .......................................................................... 58 i 2 c interface ............................................................................... 58 start, stop, and repeated start conditions ................................................. 58 slave address ........................................................................... 59 bit transfer .............................................................................. 59 single-byte write ......................................................................... 60 burst write .............................................................................. 60 single-byte read ......................................................................... 61 burst read .............................................................................. 61 acknowledge bits ........................................................................ 62 applications information ........................................................................ 62 startup and initialization ...................................................................... 62 low-power operation ........................................................................ 63 interrupts and polling ........................................................................ 63 logic-level translation ....................................................................... 63 power-supply sequencing .................................................................... 64 connector sharing .......................................................................... 64 rs-232 5x3 application ...................................................................... 64 typical application circuit ...................................................................... 65 chip information .............................................................................. 65 package information ........................................................................... 65 revision history .............................................................................. 66 table of contents ( continued ) max3109
4 ______________________________________________________________________________________ dual serial uart with 128-word fifos figure 1. i 2 c timing diagram .................................................................... 12 figure 2. spi timing diagram ................................................................... 12 figure 3. transmit fifo signals .................................................................. 17 figure 4. receive data format ................................................................... 17 figure 5. receive fifo ........................................................................ 18 figure 6. midbit sampling ...................................................................... 18 figure 7. clock selection diagram ................................................................ 19 figure 8. 2x and 4x baud rates .................................................................. 20 figure 9. gpio_ clock pulse generator ............................................................ 20 figure 10. auto transceiver direction control ....................................................... 22 figure 11. setup and hold times in auto transceiver direction control ................................... 22 figure 12. single transmitter trigger accuracy ...................................................... 23 figure 13. multiple transmitter synchronization accuracy .............................................. 23 figure 14. half-duplex with echo suppression ...................................................... 24 figure 15. echo suppression timing .............................................................. 25 figure 16. simplified interrupt structure ............................................................ 27 figure 17. pll signal path ...................................................................... 49 figure 18. spi write cycle ...................................................................... 57 figure 19. spi ready cycle ..................................................................... 57 figure 20. spi fast read cycle .................................................................. 58 figure 21. i 2 c start, stop, and repeated start conditions ......................................... 59 figure 22. write byte sequence .................................................................. 60 figure 23. burst write sequence ................................................................. 60 figure 24. read byte sequence ................................................................. 61 figure 25. burst read sequence ................................................................. 61 figure 26. acknowledge ....................................................................... 62 figure 27. startup and initialization flowchart . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62 figure 28. logic-level translation ................................................................ 63 figure 29. connector sharing with a usb transceiver ................................................ 64 figure 30. rs-232 application ................................................................... 64 figure 31. rs-485 half-duplex application ......................................................... 65 list of figures max3109
_______________________________________________________________________________________ 5 dual serial uart with 128-word fifos table 1. stopbits truth table .................................................................... 40 table 2. lengthx truth table .................................................................... 40 table 3. swflow[3:0] truth table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 table 4. pllfactorx selection guide .............................................................. 49 table 5. globlcomnd command descriptions ...................................................... 53 table 6. extended mode addressing (spi only) ..................................................... 53 table 7. spi command byte configuration ......................................................... 57 table 8. i 2 c address map ...................................................................... 59 receive hold register (rhr) .................................................................... 29 transmit hold register (thr) .................................................................... 29 irq enable register (irqen) .................................................................... 30 interrupt status register (isr) ................................................................... 31 line status interrupt enable register (lsrinten) ..................................................... 32 line status register (lsr) ...................................................................... 33 special character interrupt enable register (spclchrinten) ............................................ 34 special character interrupt register (spclcharint) ................................................... 35 sts interrupt enable register (stsinten) .......................................................... 36 status interrupt register (stsint) ................................................................. 37 mode1 register .............................................................................. 38 mode2 register ............................................................................. 39 line control register (lcr) ..................................................................... 40 receiver timeout register (rxtimeout) ........................................................... 41 hdplxdelay register .......................................................................... 41 irda register ................................................................................ 42 flow level register (flowlvl) .................................................................... 42 fifo interrupt trigger level register (fifotrglvl) ................................................... 43 transmit fifo level register (txfifolvl) .......................................................... 43 receive fifo level register (rxfifolvl) .......................................................... 43 flow control register (flowctrl) .................................................................. 44 xon1 register ............................................................................... 45 xon2 register ............................................................................... 46 xoff1 register .............................................................................. 46 xoff2 register .............................................................................. 47 gpio configuration register (gpioconfg) ......................................................... 47 list of tables list of registers max3109
6 ______________________________________________________________________________________ dual serial uart with 128-word fifos list of registers ( continued ) gpio data register (gpiodata) ................................................................. 48 pll configuration register (pllconfig) ........................................................... 49 baud-rate generator configuration register (brgconfig) ............................................. 50 baud-rate generator lsb divisor register (divlsb) ................................................. 50 baud-rate generator msb divisor register (divmsb) ................................................ 51 clock source register (clksource) .............................................................. 51 global irq register (globalirq) ................................................................. 52 global command register (globlcomnd) .......................................................... 53 transmitter synchronization register (txsynch) ..................................................... 54 synchronization delay register 1 (synchdelay1) .................................................... 55 synchronization delay register 2 (synchdelay2) .................................................... 55 timer register 1 (timer1) ...................................................................... 56 timer register 2 (timer2) ...................................................................... 56 revision identification register (revid) ............................................................ 56 max3109
_______________________________________________________________________________________ 7 dual serial uart with 128-word fifos stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. these are stress rating s only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specificatio ns is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. (voltages referenced to agnd.) v l , v cc , v ext , xin ............................................... -0.3v to +4.0v xout ........................................................ -0.3v to (v cc + 0.3v) v 18 ...................... -0.3v to the lesser of (v cc + 0.3v) and 2.0v rst , irq , mosi/a1, cs /a0, sclk/scl, miso/sda, ldoen, spi/ i2c .................... -0.3v to (v l + 0.3v) tx_, rx_, cts_ , gpio_ ........................... -0.3v to (v ext + 0.3v) dgnd ................................................................... -0.3v to +0.3v continuous power dissipation (t a = +70 n c) tqfn (derate 34.5mw/ n c above +70 n c) .............. 2758.6mw operating temperature range .......................... -40 n c to +85 n c maximum junction temperature ..................................... +150 n c storage temperature range ............................ -65 n c to +150 n c lead temperature (soldering, 10s) ................................ +300 n c soldering temperature (reflow) ...................................... +260 n c tqfn junction-to-ambient thermal resistance ( b ja ) ........... 47 n c/w junction-to-case thermal resistance ( b jc ) ............... 1.7 n c/w dc electrical characteristics (v cc = 1.71v to 3.6v, v l = 1.71v to 3.6v, v ext = 1.71v to 3.6v, t a = -40 n c to +85 n c, unless otherwise noted. typical values are at v cc = 2.8v, v l = 1.8v, v ext = 2.5v, t a = +25 n c.) (notes 2, 3) note 1: package thermal resistances were obtained using the method described in jedec specification jesd51-7, using a four- layer board. for detailed information on package thermal considerations, refer to www.maxim-ic.com/thermal-tutorial . absolute maximum ratings package thermal characteristics ( note 1) parameter symbol conditions min typ max units digital interface supply voltage v l 1.71 3.6 v analog supply voltage v cc internal pll disabled and bypassed 1.71 3.6 v internal pll enabled 2.35 3.6 uart interface logic supply voltage v ext 1.71 3.6 v logic supply voltage v 18 1.65 1.95 v current consumption v cc supply current i cc 1.8mhz crystal oscillator active, pll disabled, spi/i 2 c interface idle, uart interfaces idle, ldoen = high 500 f a baud rate = 1mbps, 20mhz external clock, spi/i 2 c interface idle, pll disabled, all uarts in loopback mode, ldoen = low 500 v 18 input power-supply current in shutdown mode i 18shdn rst = low, all inputs and outputs are idle 100 f a v cc + v l + v a shutdown supply current i shdn rst = low, miso, sclk, mosi, spi_i2c, cs , ldoen = 0/v l , ctsb0/1 = 0/v ext , ctsb0/1 = 0/v ext 0 1 f a max3109
8 ______________________________________________________________________________________ dual serial uart with 128-word fifos dc electrical characteristics ( continued ) (v cc = 1.71v to 3.6v, v l = 1.71v to 3.6v, v ext = 1.71v to 3.6v, t a = -40 n c to +85 n c, unless otherwise noted. typical values are at v cc = 2.8v, v l = 1.8v, v ext = 2.5v, t a = +25 n c.) (notes 2, 3) parameter symbol conditions min typ max units v 18 input power-supply current i 18 baud rate = 1mbps, 20mhz external clock, pll disabled, uart in loopback mode, ldoen = low (note 4) 4 ma sclk/scl, miso/sda miso/sda output logic-low voltage in i 2 c mode v oli2c sink current = 3ma, v l > 2v 0.4 v sink current = 3ma, v l < 2v 0.2 x v l miso/sda output low voltage in spi mode v olspi sink current = 2ma 0.4 v miso/sda output high voltage in spi mode v ohspi source current = 2ma v l - 0.4 v input logic-low voltage v il spi and i 2 c mode 0.3 x v l v input logic-high voltage v ih spi and i 2 c mode 0.7 x v l v input hysteresis v hyst spi and i 2 c mode 0.05 x v l v input leakage current i il v in = 0 to v l, spi and i 2 c mode -1 +1 f a input capacitance c in spi and i 2 c mode 5 pf spi/ i2c , cs /a0, mosi/a1 inputs input logic-low voltage v il spi and i 2 c mode 0.3 x v l v input logic-high voltage v ih spi and i 2 c mode 0.7 x v l v input hysteresis v hyst spi and i 2 c mode 50 mv input leakage current i il v in = 0 to v l , spi and i 2 c mode -1 +1 f a input capacitance c in spi and i 2 c mode 5 pf irq output (open drain) output logic-low voltage v ol sink current = 2ma 0.4 v output leakage current i ol v irq = 0 to v l , irq is not asserted -1 +1 f a ldoen and rst inputs input logic-low voltage v il 0.3 x v l v input logic-high voltage v ih 0.7 x v l v input hysteresis v hyst 50 mv input leakage current i il v in = 0 to v l -1 +1 f a max3109
_______________________________________________________________________________________ 9 dual serial uart with 128-word fifos dc electrical characteristics ( continued ) (v cc = 1.71v to 3.6v, v l = 1.71v to 3.6v, v ext = 1.71v to 3.6v, t a = -40 n c to +85 n c, unless otherwise noted. typical values are at v cc = 2.8v, v l = 1.8v, v ext = 2.5v, t a = +25 n c.) (notes 2, 3) parameter symbol conditions min typ max units uart interface rts_ , tx_ outputs output logic-low voltage v ol sink current = 2ma 0.4 v output logic-high voltage v oh source current = 2ma 0.7 x v ext v input leakage current i il output is three-stated, v rts = 0 to v ext -1 +1 f a input capacitance c in high-z mode 5 pf cts_ , rx_ inputs input logic-low voltage v il 0.3 x v ext v input logic-high voltage v ih 0.7 x v ext v input hysteresis v hyst 50 mv cts_ input leakage current i il v cts_ = 0 to v ext -1 +1 f a rx_ pullup current i pu v rx_ = 0v -7.5 -5.5 -3.5 f a input capacitance c in 5 pf gpio_ inputs/outputs output logic-low voltage v ol sink current = 20ma, push-pull or open- drain output type, v ext > 2.3v 0.45 v sink current = 20ma, push-pull or open- drain output type, v ext < 2.3v 0.55 output logic-high voltage v oh source current = 5ma, push-pull output type v ext - 0.4 v input logic-low voltage v il gpio_ is configured as an input 0.4 v input logic-high voltage v ih gpio_ is configured as an input 2/3 x v ext v pulldown current i pd v gpio_ = v ext , gpio_ is configured as an input 3.5 5.5 7.5 f a xin input logic-low voltage v il 0.6 v input logic-high voltage v ih 1.2 v input capacitance c xin 16 pf xout input capacitance c xout 16 pf max3109
10 _____________________________________________________________________________________ dual serial uart with 128-word fifos ac electrical characteristics (v cc = 1.71v to 3.6v, v l = 1.71v to 3.6v, v ext = 1.71v to 3.6v t a = -40 n c to +85 n c, unless otherwise noted. typical values are at v cc = 2.8v, v l = 1.8v, v ext = 2.5v, t a = +25 n c.) (notes 2, 3) parameter symbol conditions min typ max units external cystal frequency f xosc 1 4 mhz external clock frequency f clk 0.5 35 mhz external clock duty cycle (note 5) 45 55 % baud-rate generator clock input frequency f ref (note 5) 96 mhz i 2 c bus: timing characteristics (figure 1) scl clock frequency f scl standard mode 100 khz fast mode 400 fast mode plus 1000 bus free time between a stop and start condition t buf standard mode 4.7 f s fast mode 1.3 fast mode plus 0.5 hold time for start condition and repeated start condition t hd:sta standard mode 4.0 f s fast mode 0.6 fast mode plus 0.26 low period of the scl clock t low standard mode 4.7 f s fast mode 1.3 fast mode plus 0.5 high period of the scl clock t high standard mode 4.0 f s fast mode 0.6 fast mode plus 0.26 data hold time t hd:dat standard mode 0 0.9 f s fast mode 0 0.9 fast mode plus 0 data setup time t su:dat standard mode 250 ns fast mode 100 fast mode plus 50 setup time for repeated start condition t su:sta standard mode 4.7 f s fast mode 0.2 fast mode plus 0.26 rise time of incoming sda and scl signals t r standard mode (0.3 x v l to 0.7 x v l ) (note 6) 20 + 0.1c b 1000 ns fast mode (0.3 x v l to 0.7 x v l ) (note 6) 20 + 0.1c b 300 fast mode plus 120 fall time of sda and scl signals t f standard mode (0.3 x v l to 0.7 x v l ) (note 6) 20 + 0.1c b 1000 ns fast mode (0.3 x v l to 0.7 x v l ) (note 6) 20 + 0.1c b 300 fast mode plus 120 max3109
______________________________________________________________________________________ 11 dual serial uart with 128-word fifos ac electrical characteristics ( continued ) (v cc = 1.71v to 3.6v, v l = 1.71v to 3.6v, v ext = 1.71v to 3.6v t a = -40 n c to +85 n c, unless otherwise noted. typical values are at v cc = 2.8v, v l = 1.8v, v ext = 2.5v, t a = +25 n c.) (notes 2, 3) note 2: all units are production tested at t a = +25 n c. specifications over temperature are guaranteed by design. note 3: currents entering the ic are negative and currents exiting the ic are positive. note 4: when v 18 is powered by an external voltage supply, it must have current capability above or equal to i 18 . note 5: guaranteed by design; not production tested. note 6: c b is the total capacitance of either the clock or data line of the synchronous bus in pf. parameter symbol conditions min typ max units setup time for stop condition t su:sto standard mode 4.7 f s fast mode 0.6 fast mode plus 0.26 capacitive load for sda and scl c b standard mode (note 5) 400 pf fast mode (note 5) 400 fast mode plus (note 5) 550 scl and sda i/o capacitance c i/o (note 5) 10 pf pulse width of spike suppressed t sp 50 ns spi bus: timing characteristics (figure 2) sclk clock period t ch +t cl 38.4 ns sclk pulse width high t ch 16 ns sclk pulse width low t cl 16 ns cs fall to sclk rise time t css 0 ns mosi hold time t dh 3 ns mosi setup time t ds 5 ns output data propagation delay t do 20 ns miso rise and fall times t ft 10 ns cs hold time t csh 30 ns max3109
12 _____________________________________________________________________________________ dual serial uart with 128-word fifos timing diagrams figure 1. i 2 c timing diagram figure 2. spi timing diagram sda start condition (s) start condition (s) repeated start condition (sr) stop condition (p) scl t hd:sta t su:dat t su:sta t hd:dat t hd:sta t su:sto t r t f t buf t high t low t r t f cs sclk mosi miso t csh t css t cl t ds t ft t dh t ch t do t csh max3109
______________________________________________________________________________________ 13 dual serial uart with 128-word fifos typical operating characteristics (v cc = 2.5v, v l = 2.5v, v ext = 2.5v, v ldoen = v l , uart1 in sleep mode, t a = +25c unless otherwise noted.) source current (push-pull) vs. gpio_output high voltage max3109 toc02 v oh (v) i source (ma) 3 2 1 10 20 30 40 50 60 70 0 04 v ext = 3.3v v ext = 2.5v v ext = 1.8v transmitter synchronization max3109 toc03 10s/div v scl 2v/div v tx0 2v/div 115.2kbaud v tx1 2v/div 460.8kbaud 0v 0v 0v i 2 c mode sink current (open drain) vs. gpio_ output low voltage max3109 toc01 v ol (v) i sink (ma) 3 2 1 20 40 60 80 100 120 140 160 180 0 04 v ext = 3.6v v ext = 2.5v v ext = 1.71v max3109
14 _____________________________________________________________________________________ dual serial uart with 128-word fifos pin configuration pin description tqfn (5mm 5mm) top view 29 30 28 27 12 11 13 miso/sda gpio7 cs/a0 mosi/a1 irq 14 rst gpio2 rts0 rx1 gpio3 rx0 tx0 12 gpio6 45 67 23 24 22 20 19 18 agnd ldoen gpio5 gpio1 gpio4 gpio0 sclk/scl rts1 3 21 31 10 v 18 dgnd 32 9 v cc + spi/i2c xout 26 15 cts0 xin 25 16 cts1 v l tx1 8 17 v ext *ep *connect ep to agnd. max3109 pin name function 1 rst active-low reset input. drive rst low to force all of the uarts into hardware reset mode. driving rst low also enables low-power shutdown mode. when rst is low, the internal v18 ldo is switched off, even if the ldoen input is kept high. 2 miso/sda serial-data output. when spi/ i2c is high, miso/sda functions as the spi master input-slave output (miso). when spi/ i2c is low, miso/sda functions as the sda, i 2 c serial-data input/output. miso/sda is high impedance when rst is driven low or when the externally supplied v18 is powered off. 3 sclk/scl serial-clock input. when spi/ i2c is high, sclk/scl functions as the sclk spi serial-clock input (up to 26 mhz). when spi/ i2c is low, sclk/scl functions as the scl, i 2 c serial-clock input (up to 1mhz in fast mode plus). 4 gpio7 general-purpose input/output 7. gpio7 is user-programmable as an input or output (push-pull or open drain) or an external event-driven interrupt source. gpio7 has a weak pulldown resistor to dgnd when configured as an input. 5 cs /a0 active-low chip-select and address 0 input. when spi/ i2c is high, cs /a0 functions as the cs , spi active-low chip-select. when spi/ i2c is low, cs /a0 functions as the a0 i 2 c device address programming input. connect cs /a0 to dgnd, v l , scl, or sda when spi/ i2c is low. 6 mosi/a1 serial-data input and address 1 input. when spi/ i2c is high, mosi/a1 functions as the spi master output-slave input (mosi). when spi/ i2c is low, mosi/a1 functions as the a1 i 2 c device address programming input. connect mosi/a1 to dgnd, v l , scl, or sda when spi/ i2c is low. 7 irq active-low interrupt open-drain output. irq is asserted when an interrupt is pending. irq is high impedance when rst is driven low. max3109
______________________________________________________________________________________ 15 dual serial uart with 128-word fifos pin description (continued) pin name function 8 v l digital interface power supply. v l powers the internal logic-level translators for rst , irq , mosi/a1, cs /a0, sclk/scl, miso/sda, ldoen, and spi/ i2c . bypass v l with a 0.1 f f ceramic capacitor to dgnd. 9 spi/ i2c spi selector input or active-low i 2 c. drive spi/ i2c low to enable i 2 c. drive spi/ i2c high to enable spi. 10 dgnd digital ground 11 gpio0 general-purpose input/output 0. gpio0 is user-programmable as an input or output (push-pull or open drain) or an external event-driven interrupt source. gpio0 has a weak pulldown resistor to dgnd when configured as an input. gpio0 is the reference clock output when bit 7 of the txsynch register is set to high (see the uart clock to gpio section for more information). 12 gpio4 general-purpose input/output 4. gpio4 is user-programmable as an input or output (push-pull or open drain) or an external event-driven interrupt source. gpio4 has a weak pulldown resistor to dgnd when configured as an input. gpio4 is the reference clock output when bit 7 of the txsynch register is set to high (see the uart clock to gpio section for more information). 13 gpio1 general-purpose input/output 1. gpio1 is user-programmable as an input or output (push-pull or open drain) or an external event-driven interrupt source. gpio1 has a weak pulldown resistor to dgnd when configured as an input. gpio1 is the timer output when bit 7 of the timer2 register is set high. 14 gpio5 general-purpose input/output 5. gpio5 is user-programmable as an input or output (push-pull or open drain) or an external event-driven interrupt source. gpio5 has a weak pulldown resistor to dgnd when configured as an input. gpio5 is the timer output when bit 7 of the timer2 register is set high. 15 cts0 active-low clear-to-send input for uart0. cts0 is a flow-control status input. 16 cts1 active-low clear-to-send input for uart1. cts1 is a flow-control status input. 17 tx1 serial transmitting data output for uart1. tx1 is logic-high when rst is low or when the externally supplied v18 is not powered. 18 tx0 serial transmitting data output for uart0. tx0 is logic-high when rst is low or when the externally supplied v18 is not powered. 19 rx0 serial receiving data input for uart0. rx0 has an internal weak pullup resistor to v ext . 20 rx1 serial receiving data input for uart1. rx1 has an internal weak pullup resistor to v ext . 21 rts0 active-low request-to-send output for uart0. rts0 can be set high or low by programming the lcr register. rts0 is the uart system clock/fractional divider output when bit 7 of the clksource register is set high. rts0 is logic-high when rst is low or when the externally supplied v18 is not powered. 22 rts1 active-low request-to-send output for uart1. rts1 can be set high or low by programming the lcr register. rts1 is the uart system clock/fractional divider output when bit 7 of the clksource register is set high. rts1 is logic-high when rst is low or when the externally supplied v18 is not powered. 23 gpio2 general-purpose input/output 2. gpio2 is user-programmable as input or output (push-pull or open drain) or an external event-driven interrupt source. gpio2 has a weak pulldown resistor to dgnd when configured as an input. 24 gpio3 general-purpose input/output 3. gpio3 is user-programmable as input or output (push-pull or open drain) or an external event-driven interrupt source. gpio3 has a weak pulldown resistor to dgnd when configured as an input. 25 v ext transceiver interface power supply. v ext powers the internal logic-level translators for rx_, tx_, rts_ , cts_ , and gpio_. bypass v ext with a 0.1 f f ceramic capacitor to dgnd. 26 xin crystal/clock input. when using an external crystal, connect one end of the crystal to xin and the other end to xout. when using an external clock source, drive xin with the single-ended external clock. max3109
16 _____________________________________________________________________________________ dual serial uart with 128-word fifos detailed description the max3109 dual universal asynchronous receiver- transmitter (uart) bridges an spi/microwire k or i 2 c microprocessor bus to an asynchronous serial-data communication link, such as rs-485, rs-232, or irda. the max3109 is configured through 8-bit registers, which are accessed through the spi or i 2 c interface. these registers are organized by related function as shown in the register map section. the host controller loads data into the transmit hold reg - ister ( thr ) through the spi or i 2 c interface. this data is automatically pushed into the transmit fifos, formatted, and sent out at tx_. the max3109 adds start, stop, and parity bits to the data before transmitting the data out at the selected baud rate. the clock configuration registers determine the baud rates, clock source selec - tion, clock frequency prescaling, and fractional baud- rate generator settings for each uart. the max3109 receivers detect a start bit as a high- to-low transition on rx_. an internal clock samples this data at 16 times the baud rate. the received data is automatically placed in the receive fifos and can then be read out by the host controller through the receiver hold register ( rhr ). the device features two identical uarts that are com - pletely independent except for the input clock. text in this data sheet references individual uart operation, unless otherwise noted. the max3109s register set is compatible with the max3107. refer to application note 4938: differences between maxim's advanced uart devices for information on how to transfer firmware from the max3107 to the max3109. receive and transmit fifos each uarts receiver and transmitter has a 128-word- deep fifos, reducing the number of intervals that the host processor needs to dedicate for high-speed, high- volume data transfer to and from the device. as the data rates of the asynchronous rx_/tx_ interfaces increase and get closer to those of the host controllers spi/i 2 c data rates, uart management and flow-control can make up a significant portion of the hosts activity. by increasing fifo size, the host is interrupted less often and can use data block transfers to and from the fifos. fifo trigger levels can generate interrupts to the host controller, signaling that programmed fifo fill levels have been reached. the transmitter and receiver trigger levels are programmed through the fifotrglvl register with a resolution of eight fifo locations. the receive fifo trigger signals to the host either that the receive fifo has a defined number of words waiting to be read out in a block or that a known number of vacant fifo locations are available and ready to be filled. the trans - mit fifo trigger generates an interrupt when the transmit fifo fill level is above the programmed trigger level. the host then knows to throttle data writing to the transmit fifo through thr . the host can read out the number of words pres - ent in each of the fifos through the txfifolvl and rxfifolvl registers. microwire is a trademark of national semiconductor corp. pin description (continued) pin name function 27 xout crystal output. when using an external crystal, connect one end of the crystal to xout and the other end to xin. when using an external clock source, leave xout unconnected. 28 gpio6 general-purpose input/output 6. gpio6 is user-programmable as input or output (push-pull or open drain) or an external event-driven interrupt source. gpio6 has a weak pulldown resistor to dgnd when configured as an input. 29 agnd analog ground 30 ldoen ldo enable input. drive ldoen high to enable the internal 1.8v ldo. drive ldoen low to disable the internal ldo. supply v 18 with an external voltage source when ldoen is low. 31 v 18 internal 1.8v ldo output and 1.8v power-supply input. bypass v 18 with a 0.1 f f ceramic capacitor to dgnd. 32 v cc analog power supply. v cc powers the pll and internal ldo. bypass v cc with a 0.1 f f ceramic capacitor to agnd. ep exposed pad. connect ep to agnd. do not use ep as the main agnd connection. max3109
______________________________________________________________________________________ 17 dual serial uart with 128-word fifos figure 3. transmit fifo signals the contents of the txfifo and rxfifo are both cleared when the mode2 [1]: fiforst bit is set high . transmitter operation figure 3 shows the structure of the transmitter with the txfifo. the transmit fifo can hold up to 128 words of data that are added by writing to the thr register. the current number of words in the txfifo can be read out by the host controller through the txfifolvl regis - ter. the transmit fifo fill level can be programmed to generate an interrupt when greater than or equal to a programmed number of words are present in the txfifo through the fifotrglvl register. this txfifo interrupt trigger level is selectable by the fifotrglvl [3:0] bits. when the transmit fifo fill level increases to at least the programmed trigger level, an interrupt is generated in isr [4]: txtrigint. an interrupt is generated in isr [5]: tfifoemptyint when the transmit fifo is empty. isr [5] goes high when the transmitter starts transmitting the last word in the txfifo. an additional interrupt is generated in stsint [7]: txemptyint when the transmitter completes transmitting the last word. to halt transmission, set the mode1 [1]: txdisabl bit high. after txdisabl is set, the transmitter completes the transmission of the current character and then ceases transmission. turn the transmitter off prior to enabling auto software flow control and autorts flow control. the tx_ output logic can be inverted through the irda [5]: txinv bit. unless otherwise noted, all transmitter logic described in this data sheet assumes that txinv is set low. receiver operation the receiver expects the format of the data at rx_ to be as shown in figure 4. the quiescent logic state is logic-high and the first bit (the start bit) is logic-low (rxinv = 0). the 8-bit data word expected to be received lsb first. the receiver samples the data near the midbit instant (figure 4). the received words and their associ - ated errors are deposited into the receive fifo. errors and status information are stored for every received word (figure 5). the host reads the data out of the receive fifo by reading rhr , which comes out oldest data first. after a word is read out of rhr , lsr contains the status information for that word. figure 4. receive data format current fill level transmitter tx_ transmit fifo fifotrglvl[3:0] trigger isr[4] thr data from spi/i 2 c interface 128 3 2 1 level txfifolvl empty isr[5] received data note: rxinv = 0. lsb start d0 d1 d2 d3 d4 d5 d6 d7 parity stop stop msb middata sampling max3109
18 _____________________________________________________________________________________ dual serial uart with 128-word fifos the following three error conditions are checked for each received word: parity error, frame error, and noise on the line. parity errors are detected by calculating either even or odd parity of the received word as programmed by register settings. framing errors are detected when the received data frame does not match the expected frame format in length. line noise is detected by checking the logical congruency of the three samples taken of each bit (figure 6). the receiver can be turned off by setting the mode1 [0]: rxdisabl bit high. after this bit is set high, the max3109 turns the receiver off immediately following the current word and does not receive any further data. the rx_ input logic can be inverted by setting the irda [4]: rxinv bit high. unless otherwise noted, all receiver logic described in this data sheet assumes that rxinv is set low. line noise indication when operating in standard or 2x (i.e., not 4x) rate mode, the max3109 checks that the binary logic level of the three samples per received bit are identical. if any of the three samples per received bit have differing logic levels, then noise on the transmission line has affected the received data and it is considered to be noisy. this noise indication is reflected in the lsr [5]: rxnoise bit for each received byte. parity errors are another indication of noise, but are not as sensitive. figure 5. receive fifo figure 6. midbit sampling receive fifo fifotrglvl[7:4] trigger isr[3] word error 128 rxfifolvl 4 3 2 1 timeout empty errors overrun lsr[1] received data rhr receiver rx_ i 2 c/spi interface lsr[0] isr[6] lsr[5:2] current fill level 1 rx_ baud block 23 45 67 89 one bit period 10 11 majority center sampler 12 13 14 15 16 a max3109
______________________________________________________________________________________ 19 dual serial uart with 128-word fifos clock selection the max3109 can be clocked by either an external crystal or an external clock source. figure 7 shows a simplified diagram of the clock selection circuitry. when the max3109 is clocked by a crystal, the stsint [5]: clkready bit indicates when the crystal oscillator has reached steady state and the baud-rate generator is ready for stable operation. each uart baud rate can be individually programmed and both share the same reference clock input. the baud-rate clock can be routed to the rts_ output by setting the clksource [7]: clktorts bit high. the clock rate is 16x the baud rate in standard operating mode, 8x the baud rate in 2x rate mode, and 4x the baud rate in 4x rate mode. if the fractional portion of the baud-rate gen - erator is used, the clock is not regular and exhibits jitter. crystal oscillator the max3109 is equipped with a crystal oscillator to pro - vide high baud-rate accuracy and low power consump - tion. set the clksource [1]: crystalen bit high to enable and select the crystal oscillator. the on-chip crystal oscillator has integrated load capacitances of 16pf in both the xin and xout pins. connect only an external crystal or ceramic oscillator between xin and xout. external clock source connect an external single-ended clock source to xin when not using the crystal oscillator. leave xout uncon - nected. set the clksource [1]: crystalen bit low to select external clocking. pll and predivider the internal predivider and pll allow for compatibility with a wide range of external clock frequencies and baud rates. the pll can be configured to multiply the input clock rate by a factor of 6, 48, 96, or 144 by the pllconfig [7:6] bits. the predivider is located between the input clock and the pll and allows division of the input clock by an integer factor between 1 and 63. this value is defined by the pllconfig [5:0] bits. see the pllconfig register description for more information. use of the pll requires v cc to be higher than 2.35v. fractional baud-rate generators each uart has an internal fractional baud-rate gen - erator that provides a high degree of flexibility and high resolution in baud-rate programming. the baud-rate generator has a 16-bit integer divisor and a 4-bit word for the fractional divisor. the fractional baud-rate generator can be used either with the crystal oscillator or external clock source. the integer and fractional divisors are calculated by the divisor, d: = ref f ratemode d 16 baudrate where f ref is the reference frequency input to the baud- rate generator, ratemode is the rate mode multiplier (1x default), baudrate is the desired baud rate, and d is the ideal divisor. f ref must be less than 96mhz. ratemode is 1 in 1x rate mode, 2 in 2x rate mode, and 4 in 4x rate mode. the integer divisor portion, div, of the divisor, d, is obtained by truncating d: div = trunc(d) div can be a maximum of 16 bits (65,535) wide and is programmed into the two single-byte-wide registers divmsb and divlsb . the minimum allowed value for divlsb is 1. the fractional portion of the divisor, fract, is a 4-bit nibble that is programmed into brgconfig [3:0]. the maximum value is 15, allowing the divisor to be pro - grammed with a resolution of 0.0625. fract is calcu - lated as: fract = round(16 x (d - div)). figure 7. clock selection diagram crystal oscillator xout crystalen xin fractional baud-rate generator 0 fractional baud-rate generator 1 pllbypass pllen pll divider max3109
20 _____________________________________________________________________________________ dual serial uart with 128-word fifos the following is an example of how to calculate the divi - sor. it is based on a required baud rate of 190kbaud and a reference input frequency of 28.23mhz and 1x (default) rate mode. the ideal divisor is calculated as: d = 28,230,000/(16 x 190,000) = 9.286 hence div = 9. fract = round(16 x 0.286) = 5 so divmsb = 0x00, divlsb = 0x09, and brgconfig [3:0] = 0x05. the resulting actual baud rate can be calculated as: = ref actual actual f ratemode br 16 d for this example: d actual = 9 + 5/16 = 9.3125, ratemode = 1, and br actual = 28,230,000/(16 x 9.3125) = 189463 baud. thus, the actual baud rate is within 0.28% of the ideal rate. 2x and 4x rate modes to support higher baud rates than possible with stan - dard operation using 16x sampling, the max3109 offers 2x and 4x rate modes. in these modes, the reference clock rate only needs to be either 8x or 4x higher than the baud rate, respectively. in 4x rate mode, each received bit is only sampled once at the midbit instant instead of the usual three samples to determine the logic value of the received bit. this reduces the ability to detect line noise on the received data in 4x rate mode. the 2x and 4x rate modes are selectable through brgconfig [5:4]. note that irda encoding and decoding does not operate in 2x and 4x rate modes. when 2x rate mode is selected, the actual baud rate is twice the rate programmed into the baud-rate genera - tor. if 4x rate mode is enabled, the actual baud rate on the line is quadruple that of the programmed baud rate (figure 8). low-frequency timer each uart has a general-purpose timer that can be used to generate a low-frequency clock at a gpio output and can, for example, be used to drive external leds. the low-frequency clock is a divided replica of the given uart baud-rate clock. the timer for each uart is internally routed to the respective gpio_ output when enabled by the timer2 register as follows: u uart0: gpio1 u uart1: gpio5 the clock pulses at the gpios are generated at a rate defined by the baud-rate generator and the timer divider (figure 9). the baud-rate generator clock frequency is divided by (1024 x timer[14:0]) to produce the gpio_ clock, where timer[14:0] is the 15-bit value programmed into the timer1 and timer2 registers. the timer output is 50% duty cycle clock. figure 8. 2x and 4x baud rates figure 9. gpio_ clock pulse generator fractional rate generator f ref baud rate brgconfig[5:4] divlsb divmsb note: irda does not work in 2x and 4x modes. fract 1x, 2x, 4x rate modes fractional rate generator f ref timerx gpio_ gpio_ tmrtogpio 1024 divlsb divmsb fract max3109
______________________________________________________________________________________ 21 dual serial uart with 128-word fifos uart clock to gpio the max3109 reference clock can be routed to the gpio0 and/or gpio4 outputs if a synchronous high- frequency clock is needed by another device. enable routing a uart clock to gpio0 and/or gpio4 in the txsynch register. this output clock could, for example, be used to clock another uart device. multidrop mode in multidrop mode, also known as 9-bit mode, the data word length is 8 bits and a 9th bit is used for distin - guishing between an address word and a data word. multidrop mode is enabled by the mode2 [6]: multidrop bit. the multidrop bit takes the place of the parity bit in the data word structure. parity checking is disabled and an interrupt is generated in spclcharint [5]: multidropint when an address (9th bit is 1) is received while in multi - drop mode. it is up to the host processor to filter out the data intended for its address. alternatively, the auto data-filtering fea - ture can be used to automatically filter out the data not intended for the stations specific 9-bit mode address. auto data filtering in multidrop mode in multidrop mode, the max3109 can be configured to automatically filter out data that is not meant for its address. the address is user-definable either by pro - gramming a register value or a combination of a register value and gpio hardware inputs. use either the entire xoff2 register or the xoff2 [7:4] bits in combination with gpio_ inputs to define the address. enable multidrop mode by setting the mode2 [6]: multidrop bit high and enable auto data filtering by set - ting the mode2 [4]: specialchr bit high. when using register bits in combination with gpio_ inputs to define the address, the msb of the address is written to the xoff2 [7:4] bits, while the lsbs of the address are defined by the gpios. to enable this address-definition method along with auto data filtering, set the flowctrl [2]: gpiaddr bit high in addition to the mode2 [4]: specialchr and mode2 [6]: multidrop bits. the gpio_ inputs are automatically read when the flowctrl [2]: gpiaddr bit is set high, and the address is automatically updated on logic changes to any gpio pin. when using auto data filtering, the max3109 checks each received address against the programmed station address. when an address is received that matches the stations address, received data is stored in the rxfifo. when an address is received that does not match the stations address, received data is discarded. addresses are not stored into the fifo but an inter - rupt is still generated in spclcharint [5]: multidropint upon receiving an address. an additional interrupt is generated in spclcharint [3]: xoff2int when the station address is received. auto transceiver direction control in some half-duplex communication systems, the trans - ceivers transmitter must be turned off when data is being received in order to not load the bus. this is the case in half-duplex rs-485 communication. similarly, in full-duplex multidrop communication such as rs-485 or rs-422 v.11, only one transmitter can be enabled at any one time while the others must be disabled. the max3109 can automatically enable/disable a transceivers transmit - ter and/or receiver at the hardware level by controlling its de and re pins. this feature relieves the host processor of this time-critical task. the rts_ output is used to control the transceivers transmit-enable input and is automatically set high when the max3109s transmitter starts transmission. this occurs as soon as data is present in the transmit fifo. auto transceiver direction control is enabled by the mode1 [4]: trnscvctrl bit. figure 10 shows a typical max3109 connection in an rs-485 application using the auto transceiver direction control feature. the rts output can be set high in advance of tx_ transmission by a programmable time period called the setup time (figure 11). the setup time is programmed by the hdplxdelay [7:4]: setupx bits. similarly, the rts_ output can be held high for a programmable period after the transmitter has completed transmission called the hold time. the hold time is programmed by the hdplxdelay [3:0] bits. transmitter triggering and synchronization the max3109 allows synchronization of transmitters so that selected uarts start transmitting data when a trigger command is received. optional delays can also be pro - grammed that delay the start of transmission after a trig - ger command is received. a uarts transmitter can be assigned one of 16 possible spi/i 2 c trigger commands. a trigger command is defined as any of the 16 special values written into the globlcomnd register (see the globlcomnd register description for more information). when a byte is written into the globlcomnd register, the uart select bit (u) is ignored by the max3109 and the globlcomnd applies to both uarts. transmission is initiated when the max3109 receives an assigned spi/ i 2 c trigger command, the selected transmitter is initially disabled, and data has been loaded into its txfifo. max3109
22 _____________________________________________________________________________________ dual serial uart with 128-word fifos enable and configure transmitter synchronization with the txsynch register. triggering and synchronization requires that the transmitters are disabled before the trigger is received. this can be done by setting the mode1 [1]: txdisabl bit high or by using the auto trans - mitter disable function ( txsynch [4] is logic 1). transmitter synchronization synchronize multiple uarts so that their transmitters start transmission simultaneously by assigning a com - mon trigger command to the uarts that should be synchronized. intrachip and interchip synchronization intrachip transmitter triggering occurs when the two uarts in a max3109 device are triggered by one command. this type of synchronization is supported in both spi and i 2 c modes, as the trigger commands are global commands that are received by both uarts simultaneously. interchip transmitter triggering synchronizes uarts in different max3109 devices. this type of synchroniza - tion is achievable in spi mode only. pull the cs input of all the max3109 devices on the bus low during the spi masters write trigger command so that the commands are received by all uarts on the shared spi bus. i 2 c protocol does not allow simultaneous addressing of multiple devices. delayed triggering a delay can be programmed to postpone the start of transmission after receiving an assigned trigger com - mand. set the delay by programming the synchdelay1 and synchdelay2 registers. trigger accuracy the delay between the time when the max3109 receives a trigger command and the time when the associ - ated transmitter starts transmission is made up of a fixed, deterministic portion, and a variable, random component. figure 11. setup and hold times in auto transceiver direction control figure 10. auto transceiver direction control tx_ first character last character rts_ setup hold max3109 max14840e transmitter tx_ b a d rts_ rx_ txfifo receiver auto transceiver control rxfifo di ro re de r max3109
______________________________________________________________________________________ 23 dual serial uart with 128-word fifos both portions of the delay are dependent on the uarts clock. when the fractional divider is not used, the intrinsic trigger delay, t trig , is bounded by the following limits: trig 56 t uartclk uartclk ? where uartclk is the baud-rate divider output. the reference point is the time when the trigger command is received by the max3109. this occurs on the final (i.e., the 16th) spi clocks low-to-high transition (figure 12). in i 2 c mode, this occurs on the final (i.e., the 8th) scl low-to-high transition. when the fractional baud-rate generator is used, the random portion is larger than one uart clock period. synchronization accuracy when synchronizing multiple uart transmitters, the out - put skew of the tx_ transmitter outputs is based on the triggering delays of each uart (figure 13). this skew has a baud rate dependent component, similar to the figure 12. single transmitter trigger accuracy figure 13. multiple transmitter synchronization accuracy uncertainty interval t trig_min t trig_max tx_ sclk t tx1_max t trigskew t tx1_min t tx0_max t tx0_min tx0 tx1 sclk max3109
24 _____________________________________________________________________________________ dual serial uart with 128-word fifos figure 14. half-duplex with echo suppression trigger accuracy equation for a single transmitter output. calculate the tx_ transmitter output skew using the fol - lowing equation: trigskew sf 65 t (uartclk) (uartclk) ? where (uartclk) s is the fractional divider output clock of the lower/slower baud rate uart, and (uartclk) f is the fractional divider output clock of the higher/faster baud rate uart. auto transmitter disable the max3109 allows automatic disabling of the trans - mitter. enable auto transmitter disabling functionality by setting the txsynch [6]: txautodis bit high. in this mode, the max3109 disables the specified transmitter by set - ting the mode1 [1]: txdisabl bit high after it completes sending all the data in its txfifo. new data can then be loaded into the txfifo. a disabled transmitter does not send out data on the tx_ output when data is present in its txfifo. to enable transmission after a transmitter has been dis - abled automatically, either clear the txautodis or toggle the txdisabl bit. echo suppression the max3109 can suppress echoed data that is some - times found in half-duplex communication networks, such as rs-485 and irda. if the transceivers receiver is not turned off while the transceiver is transmitting, cop - ies (echoes) of the transmitted data are received by the uart. the max3109s receiver can block the recep - tion of this echoed data by enabling echo suppression. figure 14 shows a typical rs-485 application using the echo suppression feature. set the mode2 [7]: echosuprs bit high to enable echo suppression. the max3109 can also block echoes with a long round trip delay by disabling the transceivers receiver with the rts_ output while the max3109 is transmitting. the transmitter can be configured to remain enabled after the end of the transmission for a programmable period of time called the hold time delay (figure 15). the hold time delay is set by the hdplxdelay [3:0]: holdx bits. see the hdplxdelay description in the detailed register descriptions section for more information. echo suppression can operate simultaneously with auto transceiver direction control. auto hardware flow control the max3109 is capable of auto hardware ( rts_ and cts_ ) flow control without the need for host proces - sor intervention. when autorts control is enabled, the max3109 automatically controls the rts_ hand - shake without the need for host processor intervention. autocts flow control separately turns the max3109s transmitter on and off based on the cts_ input. autorts and autocts flow control modes are independently enabled by the flowctrl [1:0] bits. autorts control autorts flow control ensures that the receive fifo does not overflow by signaling to the far-end uart to stop data transmission. the max3109 does this automatically by controlling the rts_ output. autorts flow control is enabled by setting the flowctrl [0]: autorts bit high. the halt and resume programmable values deter - mine the threshold rxfifo fill levels at which rts_ is asserted and deasserted. set the halt and resume max3109 max14840e transmitter tx_ b a d rx_ txfifo receiver echo suppression rxfifo di ro re de r rts_ max3109
______________________________________________________________________________________ 25 dual serial uart with 128-word fifos levels in the flowlvl register. with differing halt and resume levels, hysteresis of the rxfifo level can be defined for rts_ transitions. when the rxfifo is filled to a level higher than the halt level, the max3109 deasserts rts_ and stops the far- end uart from transmitting any additional data. rts_ remains deasserted until the rxfifo is emptied enough so that the number of words falls to below the resume level. interrupts are not generated when the halt and resume levels are reached. this allows the host con - troller to be completely disengaged from rts_ flow control management. autocts control when autocts flow control is enabled, the uart auto - matically starts transmitting data when the cts_ input is logic-low and stops transmitting data when cts_ is logic-high. this frees the host processor from managing this time-critical flow-control task. autocts flow con - trol is enabled by setting the flowctrl [1]: autocts bit high. the isr [7]: ctsint interrupt works normally during autocts flow control. set the irqen [7]: ctsinten bit low to disable routing of cts_ interrupts to irq and ensure that the host does not receive interrupts from cts_ transitions. if cts_ transitions from low to high during transmission of a data word, the max3109 completes the transmission of the current word and halts transmission afterwards. turn the transmitter off by setting the mode1 [1]: txdisabl bit high before enabling autocts control. auto software (xon/xoff) flow control when auto software flow control is enabled, the max3109 recognizes and/or sends predefined xon/xoff charac - ters to control the flow of data across the asynchronous serial link. the xon character signifies that there is enough room in the receive fifo and transmission of data should continue. the xoff character signifies that the receive fifo is nearing overflow and that the trans - mission of data should stop. auto software flow control works autonomously and does not require host interven - tion, similar to auto hardware flow control. to reduce the chance of receiving corrupted data that equals a single- byte xon or xoff character, the max3109 allows for double-wide (16-bit) xon/xoff characters. the xon and xoff characters are programmed into the xon1 , xon2 and xoff1 , xoff2 registers. the flowctrl [7:3] bits are used for enabling and config - uring auto software flow control. an interrupt is generated in isr [1]: spcharint whenever an xon or xoff charac - ter is received and details are stored in the spclcharint register. set the irqen [1]: spclchrien bit low to disable routing of the interrupt to irq . software flow control consists of transmit flow control and receive flow control, which operate independently of each other. receiver flow control when auto receive flow control is enabled by the flowctrl [7:6] bits, the max3109 automatically controls the transmission of data by the far-end uart by send - ing xoff and xon control characters. the halt and resume levels determine the threshold rxfifo fill levels figure 15. echo suppression timing tx_ rx_ di to ro propagation delay hold delay stop bit rts_ max3109
26 _____________________________________________________________________________________ dual serial uart with 128-word fifos at which the xoff and xon characters are sent. halt and resume are programmed in the flowlvl register. with differing halt and resume levels, hysteresis can be defined in the rxfifo fill level for the receiver flow control activity. when the rxfifo is filled to a level higher than the halt level, the max3109 sends an xoff character to stop data transmission. an xon character is sent when the rxfifo is emptied enough so that the number of words falls to below the resume level. if double-wide (16-bit) xon/xoff characters are select - ed by setting the flowctrl [7:6] bits to 11, then xon1 / xoff1 are transmitted before xon2 / xoff2 whenever a control character is transmitted. transmitter flow control if auto transmit control is enabled by the flowctrl [5:4] bits, the receiver compares all received words with the xoff and xon characters. when an xoff character is received, the max3109 halts the transmitter from sending further data following any currently transmitting word. the receiver is not affected and continues receiv - ing. upon receiving an xon character, the transmitter restarts sending data. the received xon and xoff characters are filtered out and are not stored into the receive fifo. an interrupt is not generated. if double-wide (16-bit) xon/xoff characters are select - ed by setting the flowctrl [5:4] bits to 11, then a char - acter matching xon1 / xoff1 must be received before a character matching xon2 / xoff2 in order to be inter - preted as a control character. turn the transmitter off by setting the mode1 [1]: txdisabl bit high before enabling software transmitter flow control. fifo interrupt triggering receive and transmit fifo fill-dependent interrupts are generated if fifo trigger levels are defined. when the number of words in the fifos reach or exceed a trig - ger level programmed in the fifotrglvl register, an interrupt is generated in isr [3] or isr [4]. the interrupt trigger levels operate independently from the halt and resume flow control levels in autorts or auto software flow control modes. the fifo interrupt triggering can be used, for example, for a block data transfer. the trigger level interrupt gives the host an indication that a given block size of data is available for reading in the receive fifo or available for transfer to the transmit fifo. if the halt and resume levels are outside of this range, then the uart continues to transmit or receive data during the block read/write operations for uninterrupted data transmission on the bus. low-power standby modes the max3109 has sleep and shutdown modes that reduce power consumption during periods of inactivity. in both sleep and shutdown modes, the uart disables specific functional blocks to reduce power consumption. after sleep or shutdown mode is exited, the internal clock starts up and a period of time is needed for clock stabi - lization. the stsint [5]: clkready bit indicates when the clocks are stable. when an external clock source is used, the clkready bit does not indicate clock stability. forced-sleep mode in forced-sleep mode, all uart-related on-chip clock - ing is stopped. the following blocks are inactive: the crystal oscillator, the pll, the predivider, the receiver, and the transmitter. the i 2 c/spi interface and the reg - isters remain active and the host controller can access them. to force the max3109 to enter sleep mode, set the mode1 [5]: forcedsleep bit high. to exit forced-sleep mode, set the forcedsleep bit low. auto-sleep mode the max3109 can be configured to operate in auto-sleep mode by setting the mode1 [6]: autosleep bit high. in auto-sleep mode, the max3109 automatically enters sleep mode when all the following conditions are met: ? both fifos are empty. ? there are no pending irq interrupts. ? there is no activity on any input pins for a period equal to 65,536 uart character lengths. the same blocks are inactive when the uart is in auto - sleep mode as in forced-sleep mode. the max3109 exits auto-sleep mode as soon as activity is detected on any of the gpio_, rx_, or cts_ inputs. to manually exit auto-sleep mode, set the mode1 [6]: autosleep bit low. multiple uarts in sleep mode the max3109's two uarts enter and exit sleep mode separately. when only one uart is in sleep mode, the device stops routing the clock to this uart, reducing power consumption. all other clocking circuitry remains active if the other uart is still active. if both uarts are in sleep mode, the clocking circuitry is switched off, fur - ther reducing power consumption. max3109
______________________________________________________________________________________ 27 dual serial uart with 128-word fifos shutdown mode drive the rst input to logic-low to enter shutdown mode. shutdown mode consumes less than 1 f a. in shutdown mode, all the max3109 circuitry is completely off. this includes the i 2 c/spi interface, the registers, the fifos, and the clocking circuitry. when the rst input transitions from low to high, the max3109 exits shutdown mode and a hardware reset is initiated. the chip initialization is complete when the i 2 c/spi controller is able to read out known register con - tents from the max3109. this could, for example, be the divlsb register. the max3109 needs to be reprogrammed following a shutdown. power-up and irq the irq output only operates when all supplies are active. irq operates as a hardware active-low interrupt output; irq is asserted when an interrupt is pending. an irq interrupt is only possible during normal operation if at least one of the interrupt enable bits in the irqen register is set. in polled mode, any register with a known reset value can be polled to check whether the max3109 is ready for operation. if the controller gets a valid response from the polled register, then the max3109 is ready for operation. interrupt structure figure 16 shows the structure of the interrupt. there are four interrupt source registers: isr , lsr , stsint , and spclcharint . the interrupt sources are divided into top- level and low-level interrupts. the top-level interrupts typically occur more often and can be read out by the host controller directly through isr . the low-level inter - rupts typically occur less often and their specific source can be read out by the host controller through lsr , stsint , or spclcharint . the three lsbs of isr point to the low-level interrupt registers that contain the details of the interrupt source. interrupt enabling every interrupt bit of the four interrupt registers can be enabled or masked through an associated interrupt enable register bit. these are the irqen , lsrinten , spclchrinten , and stsinten registers. by default, all interrupts are masked. interrupt clearing when an interrupt is pending (i.e., irq is asserted) and isr is read, both the isr bits are cleared and the irq output is deasserted. low-level interrupt information does not reassert irq for the same interrupt, but remains stored in the low-level interrupt registers until each is separately cleared. spclcharint and stsint are clear- on-read (cor). the lsr bits are only cleared when the source of the interrupt is removed, not when lsr is read. figure 16. simplified interrupt structure 0 0 0 0 0 0 irq1 irq0 globalirq 8 7 6 5 4 3 2 1 0 isr 7 6 5 4 3 2 1 0 isr 8 [1] irq [0] low-level interrupts top-level interrupts 7 6 5 4 3 2 1 0 spclcharint 8 7 6 5 4 3 2 1 0 stsint 8 7 6 5 4 3 2 1 0 lsr 8 max3109
28 _____________________________________________________________________________________ dual serial uart with 128-word fifos register map ( note: all default reset values are 0x00, unless otherwise noted. all registers are r/w, unless otherwise noted.) 1 denotes nonread/write mode: rhr = r, thr = w, isr = cor, lsr = r, spclcharint = cor, stsint = r/cor, txfifolvl = r, rxfifolvl = r, globalirq = r, globlcomnd = w, revid = r. 2 denotes nonzero default reset value: isr = 0x60, lcr = 0x05, fifotrglvl = 0xff, pllconfig = 0x01, divlsb = 0x01, clksource = 0x18, globalirq = 0x03, revid = 0xc1. 3 each uart has four individually assigned gpio outputs as follows: uart0: gpio0 C gpio3, uart1: gpio4 C gpio7. 4 denotes a register that can only be programmed by accessing uart0. 5 denotes a register that can only be directly addressed in i 2 c mode. use extended addressing when operating in spi mode. register addr bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 fifo data rhr 1 0x00 rdata7 rdata6 rdata5 rdata4 rdata3 rdata2 rdata1 rdata0 thr 1 0x00 tdata7 tdata6 tdata5 tdata4 tdata3 tdata2 tdata1 tdata0 interrupts irqen 0x01 ctsien rxemtyien tfifoemtyien txtrgien rxtrgien stsien spchrien lsrerrien isr 1, 2 0x02 ctsint rxemptyint tfifoemptyint txtrgint rxtrigint stsint spcharint lsrerrint lsrinten 0x03 noiseinten rbreakien frameerrien parityien roverrien rtimoutien lsr 1, 2 0x04 cts bit rxnoise rxbreak frameerr rxparityerr rxoverrun rtimeout spclchrinten 0x05 mltdrpinten breakinten xoff2inten xoff1inten xon2inten xon1inten spclcharint 1 0x06 multidropint breakint xoff2int xoff1int xon2int xon1int stsinten 3 0x07 txemptyinten sleepinten clkrdyinten gpi3inten gpi2inten gpi1inten gpi0inten stsint 1, 2, 3 0x08 txemptyint sleepint clkready gpi3int gpi2int gpi1int gpi0int uart modes mode1 0x09 irqsel autosleep forcedsleep trnscvctrl rtshiz txhiz txdisabl rxdisabl mode2 0x0a echosuprs multidrop loopback specialchr rfifoemptyinv rxtrginv fiforst rst lcr 2 0x0b rts bit txbreak forceparity evenparity parityen stopbits length1 length0 rxtimeout 0x0c timout7 timout6 timout5 timout4 timout3 timout2 timout1 timout0 hdplxdelay 0x0d setup3 setup2 setup1 setup0 hold3 hold2 hold1 hold0 irda 0x0e txinv rxinv mir sir irdaen fifos control flowlvl 0x0f resume3 resume2 resume1 resume0 halt3 halt2 halt1 halt0 fifotrglvl 2 0x10 rxtrig3 rxtrig2 rxtrig1 rxtrig0 txtrig3 txtrig2 txtrig1 txtrig0 txfifolvl 1 0x11 txfl7 txfl6 txfl5 txfl4 txfl3 txfl2 txfl1 txfl0 rxfifolvl 1 0x12 rxfl7 rxfl6 rxfl5 rxfl4 rxfl3 rxfl2 rxfl1 rxfl0 flow control flowctrl 0x13 swflow3 swflow2 swflow1 swflow0 swflowen gpiaddr autocts autorts xon1 0x14 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 xon2 0x15 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 xoff1 0x16 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 xoff2 0x17 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 gpios gpioconfg 3 0x18 gp3od gp2od gp1od gp0od gp3out gp2out gp1out gp0out gpiodata 3 0x19 gpi3dat gpi2dat gpi1dat gpi0dat gpo3dat gpo2dat gpo1dat gpo0dat clock configuration pllconfig 2, 4 0x1a pllfactor1 pllfactor0 prediv5 prediv4 prediv3 prediv2 prediv1 prediv0 brgconfig 0x1b 4xmode 2xmode fract3 fract2 fract1 fract0 divlsb 2 0x1c div7 div6 div5 div4 div3 div2 div1 div0 divmsb 0x1d div15 div14 div13 div12 div11 div10 div9 div8 clksource 2, 4 0x1e clktorts pllbypass pllen cystalen global registers globalirq 1, 2 0x1f 0 0 0 0 0 0 irq1 irq0 globlcomnd 1 0x1f glbcom7 glbcom6 glbcom5 glbcom4 glbcom3 glbcom2 glbcom1 glbcom0 synchronization txsynch 5 0x20 clktogpio txautodis trigdelay synchen trigsel3 trigsel2 trigsel1 trigsel0 synchdelay1 5 0x21 sdelay7 sdelay6 sdelay5 sdelay4 sdelay3 sdelay2 sdelay1 sdelay0 synchdelay2 5 0x22 sdelay15 sdelay14 sdelay13 sdelay12 sdelay11 sdelay10 sdelay9 sdelay8 timer registers timer1 5 0x23 timer7 timer6 timer5 timer4 timer3 timer2 timer1 timer0 timer2 5 0x24 tmrtogpio timer14 timer13 timer12 timer11 timer10 timer9 timer8 revision revid 1, 2, 5 0x25 1 1 0 0 0 0 0 1 max3109
______________________________________________________________________________________ 29 dual serial uart with 128-word fifos detailed register descriptions the max3109 has 8-bit-wide registers. when using spi control, the extended register location (0x20 through 0x25) can only be accessed by first enabling extended read/writing through globlcomnd . each uart has an exclusive set of registers. select a uart to write to by setting the u bit of the command byte in spi mode or the unique i 2 c address in i 2 c mode (see the serial controller interface section for more information). receive hold register (rhr) bits 7C0: rdatax the rhr is the bottom of the receive fifo and is the register used for reading data out of the receive fifo. it contains the oldest (first received) character in the receive fifo. rhr [0] is the lsb of the character received at the rx_ input. it is the first data bit of the serial-data word received by the receiver. reading rhr removes the read word from the receive fifo, clearing space for more data to be received. transmit hold register (thr) bits 7C0: tdatax the thr is the register that the host controller writes data to for subsequent uart transmission. this data is depos - ited in the transmit fifo. thr [0] is the lsb. it is the first data bit of the serial-data word that the transmitter sends out, immediately after the start bit. address: 0x00 mode: r bit 7 6 5 4 3 2 1 0 name rdata7 rdata6 rdata5 rdata4 rdata3 rdata2 rdata1 rdata0 reset 0 0 0 0 0 0 0 0 address: 0x00 mode: w bit 7 6 5 4 3 2 1 0 name tdata7 tdata6 tdata5 tdata4 tdata3 tdata2 tdata1 tdata0 reset 0 0 0 0 0 0 0 0 max3109
30 _____________________________________________________________________________________ dual serial uart with 128-word fifos irq enable register (irqen) the irqen register is used to enable the irq physical interrupt. any of the eight isr interrupt sources can be enabled to generate an interrupt on irq . the irqen bits only influence the irq output and do not have any effect on the isr contents or behavior. every one of the irqen bits operates on a corresponding isr bit. bit 7: ctsien the ctsien bit enables irq interrupt generation when the ctsint interrupt is set in isr [7]. set ctsien low to disable irq generation from ctsint. bit 6: rxemtyien the rxemtyien bit enables irq interrupt generation when the rxemptyint interrupt is set in isr [6]. set rxemtyien low to disable irq generation from rxemptyint. bit 5: tfifoemtyien the tfifoemtyien bit enables irq interrupt generation when the tfifoemptyint interrupt is set in isr [5]. set tfifoemtyien low to disable irq generation from tfifoemptyint. bit 4: txtrgien the txtrgien bit enables irq interrupt generation when the txtrigint interrupt is set in isr [4]. set txtrgien low to disable irq generation from txtrigint. bit 3: rxtrgien the rxtrgien bit enables irq interrupt generation when the rxtrigint interrupt is set in isr [3]. set rxtrgien low to disable irq generation from rxtrigint. bit 2: stsien the stsien bit enables irq interrupt generation when the stsint interrupt is set in isr [2]. set stsien low to disable irq generation from stsint. bit 1: spchrien the spchrien bit enables irq interrupt generation when the spcharint interrupt is set in isr [1]. set spchrien low to disable irq generation from spcharint. bit 0: lsrerrien the lsrerrien bit enables irq interrupt generation when the lsrerrint interrupt is set in isr [0]. set lsrerrien low to disable irq generation from lsrerrint. address: 0x01 mode: r/w bit 7 6 5 4 3 2 1 0 name ctsien rxemtyien tfifoemtyien txtrgien rxtrgien stsien spchrien lsrerrien reset 0 0 0 0 0 0 0 0 max3109
______________________________________________________________________________________ 31 dual serial uart with 128-word fifos interrupt status register (isr) the interrupt status register provides an overview of all interrupts generated by the max3109. both the interrupt bits and any pending interrupts on irq are cleared after reading isr . when the max3109 is operated in polled mode, isr can be polled to establish the uarts status. in interrupt-driven mode, irq interrupts are enabled by the appropriate irqen bits. the isr contents either give direct information on the cause for the interrupt or point to other registers that contain more detailed information. bit 7: ctsint the ctsint interrupt is generated when a logic state transition occurs at the cts_ input. ctsint is cleared after isr is read. the current logic state of the cts_ input can be read out through the lsr [7]: cts bit bit. bit 6: rxemptyint the rxemptyint interrupt is generated when the receive fifo is empty. rxemptyint is cleared after isr is read. its meaning can be inverted by the mode2 [3]: rfifoemptyinv bit. bit 5: tfifoemptyint the tfifoemptyint interrupt is generated when the transmit fifo is empty and the transmitter is transmitting the last character. use stsint [7]: txemptyint to determine when the last character has completed transmission. tfifoemptyint is cleared after isr is read. bit 4: txtrigint the txtrigint interrupt is generated when the number of characters in the transmit fifo is equal to or greater than the transmit fifo trigger level defined in fifotrglvl [3:0]. txtrigint is cleared when the transmit fifo level falls below the trigger level or after isr is read. txtrigint can be used as a warning that the transmit fifo is nearing overflow. bit 3: rxtrigint the rxtrigint interrupt is generated when the receive fifo fill level reaches the receive fifo trigger level defined in fifotrglvl [7:4]. rxtrigint can be used as an indication that the receive fifo is nearing overrun. it can also be used to report that a known number of words are available that can be read out in one block. the meaning of rxtrigint can be inverted by the mode2 [2]: rxtriginv bit. rxtrigint is cleared after isr is read. bit 2: stsint the stsint interrupt is generated when any interrupt in the stsint register that is enabled by a stsinten bit is high. stsint is cleared after isr is read, but the interrupt in stsint that caused this interrupt remains set. see the stsint register description for details about this interrupt. bit 1: spcharint the spcharint interrupt is generated when a special character is received, a line break is detected, or an address character is received in multidrop mode. spcharint is cleared after isr is read, but the interrupt in spclcharint that caused this interrupt remains set. see the spclcharint register description for details about this interrupt. bit 0: lsrerrint the lsrerrint interrupt is generated when any interrupts in lsr that are enabled by corresponding bits in lsrinten are set. this bit is cleared after isr is read. see the lsr register description for details about this interrupt. address: 0x02 mode: cor bit 7 6 5 4 3 2 1 0 name ctsint rxemptyint tfifoemptyint txtrigint rxtrigint stsint spcharint lsrerrint reset 0 1 1 0 0 0 0 0 max3109
32 _____________________________________________________________________________________ dual serial uart with 128-word fifos line status interrupt enable register (lsrinten) lsrinten allows routing of lsr interrupts to isr [0]. the lsrinten bits only influence the isr [0]: lsrerrint bit and do not have any effect on the lsr contents or behavior. bits 5 to 0 of the lsrinten register operate on a corresponding lsr bit, while bits 7 and 6 are not used. bits 7 and 6: no function bit 5: noiseinten set the noiseinten bit high to enable routing the lsr [5]: rxnoise interrupt to isr [0]. if noiseinten is set low, rxnoise is not routed to isr [0]. bit 4: rbreakien set the rbreakien bit high to enable routing the lsr [4]: rxbreak interrupt to isr [0]. if rbreakien is set low, rxbreak is not routed to isr [0]. bit 3: frameerrien set the frameerrien bit high to enable routing the lsr [3]: frameerr interrupt to isr [0]. if frameerrien is set low, frameerr is not routed to isr [0]. bit 2: parityien set the parityien bit high to enable routing the lsr [2]: rxparityerr interrupt to isr [0]. if parityien is set low, rxparityerr is not routed to isr [0]. bit 1: roverrien set the roverrien bit high to enable routing the lsr [1]: rxoverrun interrupt to isr [0]. if roverrien is set low, rxoverrun is not routed to isr [0]. bit 0: rtimoutien set the rtimoutien bit high to enable routing the lsr [0]: rtimeout interrupt to isr [0]. if rtimoutien is set low, rtimeout is not routed to isr [0]. address: 0x03 mode: r/w bit 7 6 5 4 3 2 1 0 name noiseinten rbreakien frameerrien parityien roverrien rtimoutien reset 0 0 0 0 0 0 0 0 max3109
______________________________________________________________________________________ 33 dual serial uart with 128-word fifos line status register (lsr) lsr contains all error information related to the word most recently read out from the rxfifo through rhr . the lsr bits are not cleared after lsr is read; these bits stay set until the next character is read out of rhr , with the exception of lsr [1], which is cleared by reading either rhr or lsr . lsr also contains the current logic state of the cts input. bit 7: cts bit the cts bit bit reflects the current logic state of the cts_ input. this bit is cleared when the cts_ input is low and set when it is high. following a power-up or reset, the logic state of cts bit depends on the state of the cts_ input. bit 6: no function bit 5: rxnoise if noise is detected on the rx_ input during reception of a character, the rxnoise interrupt is generated for that char - acter. lsr [5] corresponds to the character most recently read from rhr . rxnoise is cleared after the character fol - lowing the noisy character is read out from rhr . rxnoise generates an interrupt in isr [0] if enabled by lsrinten [5]. bit 4: rxbreak if a line break (rx input low for a period longer than the programmed character duration) is detected, a break character is put in the rxfifo and the rxbreak interrupt is generated for this character. a break character is represented by an all-zeros data character. the rxbreak interrupt distinguishes a regular character with all zeros from a break character. lsr [4] corresponds to the current character most recently read from rhr . rxbreak is cleared after the character fol - lowing the break character is read out from rhr . rxbreak generates an interrupt in isr [0] if enabled by lsrinten [4]. bit 3: frameerr the frameerr interrupt is generated when the received data frame does not match the expected frame format in length. a frame error is related to errors in expected stop bits. lsr [3] corresponds to the frame error of the character most recently read from rhr . frameerr is cleared after the character following the affected character is read out from rhr . frameerr generates an interrupt in isr [0] if enabled by lsrinten [3]. bit 2: rxparityerr the rxparityerr interrupt is generated when the parity computed on the character being received does not match the received characters parity bit. lsr [2] indicates a parity error for the character most recently read from rhr . rxparityerr is cleared when the character following the affected character is read out from rhr . in 9-bit multidrop mode ( mode2 [6] is logic 1) the receiver does not check parity and the 9th bit (address/data) is stored in lsr [2]. rxparityerr generates an interrupt in isr [0] if enabled by lsrinten [2]. bit 1: rxoverrun the rxoverrun interrupt is generated when the receive fifo is full and additional data is received that does not fit into the receive fifo. the receive fifo retains the data that it already contains and discards all new data. rxoverrun is cleared after lsr is read or the rxfifo level falls below its maximum. rxoverrun generates an interrupt in isr [0] if enabled by lsrinten [1]. bit 0: rtimeout the rtimeout interrupt indicates that stale data is present in the receive fifo. rtimeout is set when all of the char - acters in the rxfifo have been present for at least as long as the period programmed into the rxtimeout register. address: 0x04 mode: r bit 7 6 5 4 3 2 1 0 name cts bit rxnoise rxbreak frameerr rxparityerr rxoverrun rtimeout reset x 0 0 0 0 0 0 0 max3109
34 _____________________________________________________________________________________ dual serial uart with 128-word fifos the timeout counter restarts whenever rhr is read or a new character is received by the rxfifo. if the value in rxtimeout is zero, rtimeout is disabled. rtimeout is cleared after a word is read out of the rxfifo or a new word is received. rtimeout generates an interrupt in isr [0] if enabled by lsrinten [0]. special character interrupt enable register (spclchrinten) spclchrinten allows routing of spclcharint interrupts to isr [1]. the spclchrinten bits only influence the isr [1]: spcharint bit and do not have any effect on the spclcharint contents or behavior. bits 7 and 6: no function bit 5: mltdrpinten set the mltdrpinten bit high to enable routing the spclcharint [5]: multidropint interrupt to isr [1]. if mltdrpinten is set low, multidropint is not routed to isr [1]. bit 4: breakinten set the breakinten bit high to enable routing the spclcharint [4]: breakint interrupt to isr [1]. if breakinten is set low, breakint is not routed to isr [1]. bit 3: xoff2inten set the xoff2inten bit high to enable routing the spclcharint [3]: xoff2int interrupt to isr [1]. if xoff2inten is set low, xoff2int is not routed to isr [1]. bit 2: xoff1inten set the xoff1inten bit high to enable routing the spclcharint [2]: xoff1int interrupt to isr [1]. if xoff1inten is set low, xoff1int is not routed to isr [1]. bit 1: xon2inten set the xon2inten bit high to enable routing the spclcharint [1]: xon2int interrupt to isr [1]. if xon2inten is set low, xon2int is not routed to isr [1]. bit 0: xon1inten set the xon1inten bit high to enable routing the spclcharint [0]: xon1int interrupt to isr [1]. if xon1inten is set low, xon1int is not routed to isr [1]. address: 0x05 mode: r/w bit 7 6 5 4 3 2 1 0 name mltdrpinten breakinten xoff2inten xoff1inten xon2inten xon1inten reset 0 0 0 0 0 0 0 0 max3109
______________________________________________________________________________________ 35 dual serial uart with 128-word fifos special character interrupt register (spclcharint) spclcharint contains interrupts that are generated when a special character is received, an address is received in multidrop mode, or a line break occurs. bits 7 and 6: no function bit 5: multidropint the multidropint interrupt is generated when the max3109 receives an address character in 9-bit multidrop mode, enabled in mode2 [6]. multidropint is cleared after spclcharint is read. multidropint generates an interrupt in isr [1] if enabled by spclchrinten [5]. bit 4: breakint the breakint interrupt is generated when a line break (rx_ low for longer than one character length) is detected by the receiver. breakint is cleared after spclcharint is read. breakint generates an interrupt in isr [1] if enabled by spclchrinten [4]. bit 3: xoff2int the xoff2int interrupt is generated when both an xoff2 special character is received and special character detection is enabled by mode2 [4]. xoff2int is cleared after spclcharint is read. xoff2int generates an interrupt in isr [1] if enabled by spclchrinten [3]. bit 2: xoff1int the xoff1int interrupt is generated when both an xoff1 special character is received and special character detection is enabled by mode2 [4]. xoff1int is cleared after spclcharint is read. xoff1int generates an interrupt in isr [1] if enabled by spclchrinten [2]. bit 1: xon2int the xon2int interrupt is generated when both an xon2 special character is received and special character detection is enabled by mode2 [4]. xon2int is cleared after spclcharint is read. xon2int generates an interrupt in isr [1] if enabled by spclchrinten [1]. bit 0: xon1int the xon1int interrupt is generated when both an xon1 special character is received and special character detection is enabled by mode2 [4]. xon1int is cleared after spclcharint is read. xon1int generates an interrupt in isr [1] if enabled by spclchrinten [0]. address: 0x06 mode: cor bit 7 6 5 4 3 2 1 0 name multidropint breakint xoff2int xoff1int xon2int xon1int reset 0 0 0 0 0 0 0 0 max3109
36 _____________________________________________________________________________________ dual serial uart with 128-word fifos sts interrupt enable register (stsinten) stsinten allows routing of stsint interrupts to isr [2]. the stsinten bits only influence the isr [2]: stsint bit and do not have any effect on the stsint contents or behavior, with the exception of the gpixinten interrupt enable bits, which control the generation of the stsint . bit 7: txemptyinten set the txemptyinten bit high to enable routing the stsint [7]: txemptyint interrupt to isr [2]. if txemptyinten is set low, txemptyint is not routed to isr [2]. bit 6: sleepinten set the sleepinten bit high to enable routing the stsint [6]: sleepint interrupt to isr [2]. if sleepinten is set low, sleepint is not routed to isr [2]. bit 5: clkrdyinten set the clkrdyinten bit high to enable routing the stsint [6]: clkready interrupt to isr [2]. if clkrdyinten is set low, clkready is not routed to isr [2]. bit 4: no function bits 3C0: gpixinten each uart has four individually assigned gpio outputs as follows: uart0: gpio0Cgpio3, uart1: gpio4Cgpio7. for example, for uart1: gp0od configures gpio4, gp1od configures gpio5, gp2od configures gpio6 and gp3od configures gpio7. set the gpixinten bits high to enable generating the stsint [3:0]: gpixint interrupts. if any of the gpixinten bits are set low, the associated gpixint interrupts are not generated. address: 0x07 mode: r/w bit 7 6 5 4 3 2 1 0 name txemptyinten sleepinten clkrdyinten gpi3inten gpi2inten gpi1inten gpi0inten reset 0 0 0 0 0 0 0 0 max3109
______________________________________________________________________________________ 37 dual serial uart with 128-word fifos status interrupt register (stsint) bit 7: txemptyint the txemptyint interrupt is generated when both the txfifo is empty and the last character has completed transmis - sion. txemptyint is cleared after stsint is read. txemptyint generates an interrupt in isr [2] if enabled by stsinten [7]. bit 6: sleepint the sleepint status bit is generated when the max3109 enters sleep mode. sleepint is cleared when the uart exits sleep mode. this status bit is also cleared when the uart clock is disabled and is not cleared by reading stsint . sleepint generates an interrupt in isr [2] if enabled by stsinten [6]. bit 5: clkready the clkready status bit is generated when the clock, the predivider, and the pll have settled, signifying that the max3109 is ready for data communication. the clkready bit only works with the crystal oscillator. it does not work with external clocking through xin. clkready is cleared when the clock is disabled and is not cleared after stsint is read. clkready generates an inter - rupt in isr [2] if enabled by stsinten [5]. bit 4: no function bits 3C0: gpixint each uart has four individually assigned gpio outputs as follows: uart0: gpio0Cgpio3, uart1: gpio4Cgpio7. for example, for uart1: gp0od configures gpio4, gp1od configures gpio5, gp2od configures gpio6 and gp3od configures gpio7. the gpixint interrupts are generated when a change of logic state occurs on the associated gpio input. the gpixint interrupts are cleared after stsint is read. the gpixint interrupts generate an interrupt in isr [2] if enabled by the cor - responding bits in stsinten [3:0]. address: 0x08 mode: r/cor bit 7 6 5 4 3 2 1 0 name txemptyint sleepint clkready gpi3int gpi2int gpi1int gpi0int reset 0 0 0 0 0 0 0 0 max3109
38 _____________________________________________________________________________________ dual serial uart with 128-word fifos mode1 register bit 6: autosleep set the autosleep bit high to set the max3109 to automatically enter low-power sleep mode after a period of no activity (see the auto- s leep mode section). an interrupt is generated in stsint [6]: sleepint when the max3109 enters sleep mode. bit 5: forcedsleep set the forcedsleep bit high to force the max3109 into low-power sleep mode (see the forced-sleep mode section). the current sleep state can be read out through the forcedsleep bit, even when the uart is in sleep mode. bit 4: trnscvctrl set the trnscvctrl bit high to enable auto transceiver direction control mode. rts_ automatically controls the trans - ceivers transmit/receive enable/disable inputs in this mode. rts_ is logic-low so that the transceiver is in receive mode with the transmitter disabled until the txfifo contains data available for transmission, at which point rts_ is automatically set logic-high before the transmitter sends out the data. once the transmitter is empty, rts_ is automati - cally forced low again. setup and hold times for rts_ with respect to the tx_ output can be defined through the hdplxdelay register. a transmitter empty interrupt is generated in isr [5] when the txfifo is empty. bit 3: rtshiz set the rtshiz bit high to three-state rts_ . bit 2: txhiz set the txhiz bit high to three-state the tx_ output. bit 1: txdisabl set the txdisabl bit high to disable transmission. if the txdisabl bit is set high during transmission, the transmitter com - pletes sending out the current character and then ceases transmission. data still present in the transmit fifo remains in the txfifo. the tx_ output is set to logic-high after transmission. in auto transceiver direction control mode, txdisabl is high when the transmitter is completely empty. bit 0: rxdisabl set the rxdisabl bit high to disable the receiver of the selected uart so that the receiver stops receiving data. all data present in the receive fifo remains in the rxfifo. address: 0x09 mode: r/w bit 7 6 5 4 3 2 1 0 name autosleep forcedsleep trnscvctrl rtshiz txhiz txdisabl rxdisabl reset 0 0 0 0 0 0 0 0 max3109
______________________________________________________________________________________ 39 dual serial uart with 128-word fifos mode2 register bit 7: echosuprs set the echosuprs bit high to discard any data that the max3109 receives when its transmitter is busy transmit - ting. in half-duplex communication such as rs-485 and irda, this allows blocking of the locally echoed data. the receiver can block data for an extended time after the transmitter ceases transmission by programming a hold time in hdplxdelay [3:0]. bit 6: multidrop set the multidrop bit high to enable the 9-bit multidrop mode. if this bit is set, parity checking is not performed by the receiver and parity generation is not done by the transmitter. the address/data indication takes the place of the parity bit in received and transmitted data words. the parity error interrupt in lsr [2] has a different meaning in multidrop mode: it represents the 9th bit (address/data indication) that is received with each 9-bit data character. bit 5: loopback set the loopback bit high to enable internal local loopback mode. this internally connects tx_ to rx_ and also rts_ to cts_ . in local loopback mode, the tx_ output and the rx_ input are disconnected from the internal transmitter and receiver. the tx_ output is in three-state. the rts_ output remains connected to the internal logic and reflects the logic state programmed in lcr [7]. the cts_ input is disconnected from rts_ and the internal logic. cts_ thus remains in a high-impedance state. bit 4: specialchr set the specialchr bit high to enable special character detection. the receiver can detect up to four special characters, as selected in flowctrl [5:4] and defined in the xon1 , xon2 , xoff1 , and/or xoff2 registers, optionally in combina - tion with gpio_ inputs if enabled through flowctrl [2]: gpiaddr. when a special character is received, it is put into the rxfifo and a special character detect interrupt is generated in isr [1]. special character detection can be used in addition to auto xon/xoff flow control if enabled by flowctrl [3]: swflowen. in this case, xon/xoff flow control is limited to single byte xon and xoff characters ( xon1 and xoff1 ), and only two special characters can be defined ( xon2 and xoff2 ). bit 3: rfifoemtyinv set the rfifoemtyinv bit high to invert the meaning of the receiver empty interrupt in isr [6]: rxemptyint. if rfifoemtyinv is set low, rxemptyint is generated when the receive fifo is empty. if rfifoemtyinv is set high, rxemptyint is gener - ated when data is put into the empty receive fifo. bit 2: rxtriginv set the rxtriginv bit high to invert the meaning of the rxfifo triggering. if the rxtrginv bit is set low, an interrupt is generated in isr [3]: rxtrigint when the rxfifo fill level is filled up to above the trigger level programmed into fifotrglvl [7:4]. if rxtriginv is set high, an interrupt is generated in isr [3] when the rxfifo is emptied to below the trigger level programmed into fifotrglvl [7:4]. bit 1: fiforst set the fiforst bit high to clear all data contents from both the receive and transmit fifos. after a fifo reset, set fiforst low to continue normal operation. bit 0: rst set the rst bit high to initiate software reset for the selected uart in the max3109. the i 2 c/spi bus stays active dur - ing this reset; communication with the max3109 is possible while rst is set. all register bits in the selected uart are reset to their reset state and all fifos are cleared during a reset. set rst low to continue normal operation after a software reset. the max3109 requires reprogramming following a software reset. address: 0x0a mode: r/w bit 7 6 5 4 3 2 1 0 name echosuprs multidrop loopback specialchr rfifoemptyinv rxtriginv fiforst rst reset 0 0 0 0 0 0 0 0 max3109
40 _____________________________________________________________________________________ dual serial uart with 128-word fifos line control register (lcr) bit 7: rts bit the rts bit bit provides direct control of the rts_ output logic state. if rts bit is logic 1, then rts_ is logic 1; if it is logic 0, then rts_ is logic 0. rts bit only works when clksource [7]: clktorts is set low. bit 6: txbreak set the txbreak bit high to generate a line break whereby the tx_ output is held low. tx_ remains low until txbreak is set low. bit 5: forceparity the forceparity bit enables forced parity that overrides normal parity generation. set both the lcr [3]: parityen and forceparity bits high to use forced parity. in forced-parity mode, the parity bit is forced high by the transmitter if the lcr [4]: evenparity bit is low. the parity bit is forced low if evenparity is high. forced parity mode enables the transmit - ter to control the address/data bit in 9-bit multidrop communication. bit 4: evenparity set the evenparity bit high to enable even parity for both the transmitter and receiver. if evenparity is set low, odd parity is used. bit 3: parityen set the parityen bit high to enable the use of a parity bit on the tx_ and rx_ interfaces. set the parityen bit low to dis - able parity usage. if parityen is set low, then no parity bit is generated by the transmitter or expected by the receiver. if parityen is set high, the transmitter generates the parity bit whose polarity is defined in lcr [4]: evenparity, and the receiver checks the parity bit according to the same polarity. bit 2: stopbits the stopbits bit defines the number of stop bits and depends on the length of the word programmed in lcr [1:0] (table 1). for example, when stopbits is set high and the word length is 5, the transmitter generates a word with a stop bit length equal to 1.5 baud periods. under these conditions, the receiver recognizes a stop bit length greater than a one-bit duration. bits 1 and 0: lengthx the lengthx bits configure the length of the words that the transmitter generates and the receiver checks for at the asynchronous tx_ and rx_ interfaces (table 2). table 1. stopbits truth table table 2. lengthx truth table address: 0x0b mode: r/w bit 7 6 5 4 3 2 1 0 name rts bit txbreak forceparity evenparity parityen stopbits length1 length0 reset 0 0 0 0 0 1 0 1 stopbits word length stop bit length 0 5, 6, 7, 8 1 1 5 1C1.5 1 6, 7, 8 2 length1 length0 word length 0 0 5 0 1 6 1 0 7 1 1 8 max3109
______________________________________________________________________________________ 41 dual serial uart with 128-word fifos receiver timeout register (rxtimeout) bits 7C0: timoutx the rxtimeout register allows programming a time delay from after the last (newest) character in the receive fifo was received until a receive data timeout interrupt is generated in lsr [0]. the units of timoutx are measured in com - plete character frames, which are dependent on the character length, parity, and stop bit settings, and baud rate. if the value in rxtimeout equals zero, a timeout interrupt is not generated. hdplxdelay register the hdplxdelay register allows programming setup and hold times between rts_ transitions and tx_ output activity in auto transceiver direction control mode, enabled by setting the mode1 [4]: trnscvctrl bit high. the hold time can also be used to ensure echo suppression in half-duplex communication. hdplxdelay functions in 2x and 4x rate modes. bits 7C4: setupx the setupx bits define a setup time for rts_ to transition high before the transmitter starts transmission of its first char - acter in auto transceiver direction control mode, enabled by setting the mode1 [4]: trnscvctrl bit high. this allows the max3109 to account for skew times between the external transmitters enable delay and propagation delays. setupx can also be used to fix a stable state on the transmission line prior to the start of transmission. the resolution of the hdplxdelay setup time delay is one bit interval, or one over the baud rate; this delay is baud-rate dependent. the maximum delay is 15 bit intervals. bits 3C0: holdx the holdx bits define a hold time for rts_ to be held high after the transmitter ends transmission of its last character in auto transceiver direction control mode, enabled by setting the mode1 [4]: trnscvctrl bit high. rts_ transitions low after the hold time delay, which starts after the last stop bit was sent. this keeps the external transmitter enabled during the hold time duration. the holdx bits also define a delay in echo suppression mode, enabled by setting the mode2 [7]: echosuprs bit high. see the echo suppression section for more information. the resolution of the hdplxdelay hold time delay is one bit interval, or one over the baud rate. thus, this delay is baud- rate dependent. the maximum delay is 15 bit intervals. address: 0x0c mode: r/w bit 7 6 5 4 3 2 1 0 name timout7 timout6 timout5 timout4 timout3 timout2 timout1 timout0 reset 0 0 0 0 0 0 0 0 address: 0x0d mode: r/w bit 7 6 5 4 3 2 1 0 name setup3 setup2 setup1 setup0 hold3 hold2 hold1 hold0 reset 0 0 0 0 0 0 0 0 max3109
42 _____________________________________________________________________________________ dual serial uart with 128-word fifos irda register the irda register allows selection of irda sir- and mir-compliant pulse shaping at the tx_ and rx_ interfaces. it also allows inversion of the tx_ and rx_ logic, separate from whether irda pulse shaping is enabled or not. bits 7, 6, and 2: no function bit 5: txinv set the txinv bit high to invert the logic at the tx_ output. this functionality is separate from irda operation. bit 4: rxinv set the rxinv bit high to invert the logic at the rx_ input. this functionality is separate from irda operation. bit 3: mir set the mir and irdaen bits high to select irda 1.1 (mir) with 1/4th period pulse widths. bit 1: sir set the sir and irdaen bits high to select irda 1.0 pulses (sir) with 3/16th period pulse widths. bit 0: irdaen set the irdaen bit high to program the max3109 to produce irda-compliant pulses at the tx_ output and expect irda- compliant pulses at the rx_ input. if irdaen is set low, normal (non-irda) pulses are generated by the transmitter and expected by the receiver. use irdaen in conjunction with the sir or mir bits to select the pulse width. flow level register (flowlvl) flowlvl is used for selecting the rxfifo threshold levels used for auto software (xon/xoff) and hardware ( rts_ / cts_ ) flow control. bits 7C4: resumex the resumex bits set the receive fifo threshold at which an xon character is automatically sent in auto software flow control mode or rts_ is automatically asserted in autorts mode. these flow control actions occur once the rxfifo is emptied to below the value in resumex. this signals the far-end station to resume transmission. the threshold level is calculated as 8 x resumex. the resulting possible threshold-level range is 0 to 120 (decimal). bits 3C0: haltx the haltx bits set the receive fifo threshold level at which an xoff character is automatically sent in auto software flow control mode or rts_ is automatically deasserted in autorts mode. these flow control actions occur once the rxfifo is filled to above the value in haltx. this signals the far-end station to halt transmission. the threshold level is calculated as 8 x haltx. the resulting possible threshold-level range is 0 to 120 (decimal). address: 0x0e mode: r/w bit 7 6 5 4 3 2 1 0 name txinv rxinv mir sir irdaen reset 0 0 0 0 0 0 0 0 address: 0x0f mode: r/w bit 7 6 5 4 3 2 1 0 name resume3 resume2 resume1 resume0 halt3 halt2 halt1 halt0 reset 0 0 0 0 0 0 0 0 max3109
______________________________________________________________________________________ 43 dual serial uart with 128-word fifos fifo interrupt trigger level register (fifotrglvl) bits 7C4: rxtrigx the rxtrigx bits allow definition of the receive fifo threshold level at which the uart generates an interrupt in isr [3]. this interrupt can be used to signal that either the receive fifo is nearing overflow or a predefined number of fifo locations are available for being read out in one block, depending on the state of the mode2 [2]: rxtriginv bit. the selectable threshold resolution is eight fifo locations, so the actual fifo trigger level is calculated as 8 x rxtrigx. the resulting possible trigger-level range is 0 to 120 (decimal). bits 3C0: txtrigx the txtrigx bits allow definition of the transmit fifo threshold level at which the max3109 generates an interrupt in isr [4]. this interrupt can be used to manage data flow to the transmit fifo. for example, if the trigger level is defined near the bottom of the txfifo, the host knows that a predefined number of fifo locations are available for being writ - ten to in one block. alternatively, if the trigger level is set near the top of the fifo, the host is warned when the transmit fifo is nearing overflow. the selectable threshold resolution is eight fifo locations, so the actual fifo trigger level is calculated as 8 x txtrigx. the resulting possible trigger-level range is 0 to 120 (decimal). transmit fifo level register (txfifolvl) bits 7C0: txflx the txfifolvl register represents the current number of words in the transmit fifo. receive fifo level register (rxfifolvl) bits 7C0: rxflx the rxfifolvl register represents the current number of words in the receive fifo. address: 0x10 mode: r/w bit 7 6 5 4 3 2 1 0 name rxtrig3 rxtrig2 rxtrig1 rxtrig0 txtrig3 txtrig2 txtrig1 txtrig0 reset 1 1 1 1 1 1 1 1 address: 0x11 mode: r bit 7 6 5 4 3 2 1 0 name txfl7 txfl6 txfl5 txfl4 txfl3 txfl2 txfl1 txfl0 reset 0 0 0 0 0 0 0 0 address: 0x12 mode: r bit 7 6 5 4 3 2 1 0 name rxfl7 rxfl6 rxfl5 rxfl4 rxfl3 rxfl2 rxfl1 rxfl0 reset 0 0 0 0 0 0 0 0 max3109
44 _____________________________________________________________________________________ dual serial uart with 128-word fifos flow control register (flowctrl) the flowctrl register configures hardware ( rts / cts ) and software (xon/xoff) flow control as well as special char - acters detection. bits 7C4: swflowx the swflowx bits select the xon and xoff characters used for auto software flow control and/or special character detection in combination with the characters programmed in the xon1 , xon2 , xoff2 , and/or xoff2 registers. see table 3. if auto software flow control is enabled (through flowctrl [3]:swflowen) and special character detection is not enabled, swflowx allows selecting either single or dual xon/xoff character flow control. when double character flow control is enabled, the transmitter sends out xon1 / xoff1 first followed by xon2 / xoff2 during receive flow control. for transmit flow control, the receiver only recognizes the received character sequence xon1 / xoff1 followed by xon2 / xoff2 as a valid control sequence to resume/halt transmission. if only special character detection is enabled (through mode2 [4]: specialchr) while auto software flow control is dis - abled, the swflowx allows selecting either single or double character detection. single character detection allows the detection of two characters: xon1 or xon2 and xoff1 or xoff2 . double character detection does not distinguish between the sequence of the two received xon1 / xon2 or xoff1 / xoff2 characters. the two characters have to be received in succession, but it is insignificant which of the two is received first. the special characters are deposited in the receive fifo. an isr [1]: spcharint interrupt is generated when special characters are received. auto software flow control and special character detection can be enabled to operate simultaneously. if both are enabled, xon1 and xoff1 define the auto flow control characters, while xon2 and xoff2 constitute the special character detection characters. bit 3: swflowen set the swflowen bit high to enable auto software flow control. the characters used for automatic software flow control are selected by swflowx. if special character detection is enabled by setting the mode2 [4]: specialchr bit high in addition to automatic software flow control, xon1 and xoff1 are used for flow control while xon2 and xoff2 define the special characters. bit 2: gpiaddr set the gpiaddr bit high to enable the four gpio_ inputs to be used in conjunction with xoff2 for the definition of a special character. this can be used, for example, for defining the address of an rs-485 slave device through hard - ware. the gpio_ input logic levels define the four lsbs of the special character, while the four msbs are defined by the xoff2 [7:4] bits. the contents of the xoff2 [3:0] bits are neglected while the gpio_ inputs are used in special character definition. reading the xoff2 register does not reflect the logic on gpio_ in this mode. bit 1: autocts set the autocts bit high to enable autocts flow control mode. in this mode, the transmitter stops and starts sending data at the tx_ interface depending on the logic state of the cts_ input. see the auto hardware flow control sec - tion for more information about autocts flow control mode. logic changes at the cts_ input result in an interrupt in isr [7]: ctsint. the transmitter must be turned off by setting the mode1 [1]: txdisabl bit high before autocts mode is enabled. bit 0: autorts set the autorts bit high to enable autorts flow control mode. in this mode, the logic state of the rts_ output is dependent on the receive fifo fill level. the fifo thresholds at which rts_ changes state are set in flowlvl . see the auto hardware flow control section for more information about autorts flow control mode. address: 0x13 mode: r/w bit 7 6 5 4 3 2 1 0 name swflow3 swflow2 swflow1 swflow0 swflowen gpiaddr autocts autorts reset 0 0 0 0 0 0 0 0 max3109
______________________________________________________________________________________ 45 dual serial uart with 128-word fifos xon1 register the xon1 and xon2 register contents define the xon character used for automatic xon/xoff flow control and/or the special characters used for special-character detection. see the flowctrl register description for more information. bits 7C0: bitx these bits define the xon1 character if single character xon auto software flow control is enabled in flowctrl [7:4]. if double-character flow control is selected in flowctrl [7:4], these bits constitute the least significant byte of the 2-byte xon character. if special character detection is enabled in mode2 [4] and auto flow control is not enabled, these bits define a special character. if both special character detection and auto software flow control are enabled, xon1 defines the xon flow control character. table 3. swflow[3:0] truth table x = dont care address: 0x14 mode: r/w bit 7 6 5 4 3 2 1 0 name bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 reset 0 0 0 0 0 0 0 0 receive flow control transmit flow control/special character detection description swflow3 swflow2 swflow1 swflow0 0 0 0 0 no flow control/no special character detection. 0 0 x x no receive flow control. 1 0 x x transmitter generates xon1, xoff1. 0 1 x x transmitter generates xon2, xoff2. 1 1 x x transmitter generates xon1, xon2, xoff1, and xoff2. x x 0 0 no transmit flow control. x x 1 0 receiver compares xon1 and xoff1 and controls the transmitter accordingly. xon1 and xoff1 special character detection. x x 0 1 receiver compares xon2 and xoff2 and controls the transmitter accordingly. xon2 and xoff2 special character detection. x x 1 1 receiver compares xon1, xon2, xoff1, and xoff2 and controls the transmitter accordingly. xon1, xon2, xoff1, and xoff2 special character detection. max3109
46 _____________________________________________________________________________________ dual serial uart with 128-word fifos xon2 register the xon1 and xon2 register contents define the xon character for automatic xon/xoff flow control and/or the special characters used in special-character detection. see the flowctrl register description for more information. bits 7C0: bitx these bits define the xon2 character if single character auto software flow control is enabled in flowctrl [7:4]. if double-character flow control is selected in flowctrl [7:4], these bits constitute the most significant byte of the 2-byte xon character. if special character detection is enabled in mode2 [4] and auto software flow control is not enabled, these bits define a special character. if both special character detection and auto software flow control are enabled, xon2 defines a special character. xoff1 register the xoff1 and xoff2 register contents define the xoff character for automatic xon/xoff flow control and/or the special characters used in special character detection. see the flowctrl register description for more information. bits 7C0: bitx these bits define the xoff1 character if single character xoff auto software flow control is enabled in flowctrl [7:4]. if double character flow control is selected in flowctrl [7:4], these bits constitute the least significant byte of the 2-byte xoff character. if special character detection is enabled in mode2 [4] and auto software flow control is not enabled, these bits define a special character. if both special character detection and auto software flow control are both enabled, xoff1 defines the xoff flow control character. address: 0x15 mode: r/w bit 7 6 5 4 3 2 1 0 name bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 reset 0 0 0 0 0 0 0 0 address: 0x16 mode: r/w bit 7 6 5 4 3 2 1 0 name bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 reset 0 0 0 0 0 0 0 0 max3109
______________________________________________________________________________________ 47 dual serial uart with 128-word fifos xoff2 register the xoff1 and xoff2 register contents define the xoff character for automatic xon/xoff flow control and/or the special characters used in special character detection. see the flowctrl register description for more information. bits 7C0: bitx these bits define the xoff1 character if single character xoff auto software flow control is enabled in flowctrl [7:4]. if double character flow control is selected in flowctrl [7:4], these bits constitute the least significant byte of the 2-byte xoff character. if special character detection is enabled in mode2 [4] and auto software flow control is not enabled, these bits define a special character. if both special character detection and auto software flow control are both enabled, xoff2 defines a special character. gpio configuration register (gpioconfg) each uart has four gpios that can be configured as inputs or outputs and can be operated in push-pull or open-drain mode. the reference clock needs to be active for the gpios to work. each uart has four individually assigned gpio outputs as follows: uart0: gpio0Cgpio3, uart1: gpio4Cgpio7. bits 7C4: gpxod set the gpxod bits high to configure the associated gpios as open-drain outputs. set the gpxod bits low to configure the associated gpios as push-pull outputs. for example, for uart1: gp0od configures gpio4, gp1od configures gpio5, gp2od configures gpio6 and gp3od configures gpio7. the gpixdat bits reflect the input logic on the associated gpio_s. for example, for uart1: gp0dat configures gpio4, gp1dat configures gpio5, gp2dat configures gpio6 and gp3dat configures gpio7. bits 3C0: gpxout the gpxout bits configure the associated gpio_s to be either inputs or outputs. set the gpxout bits high to configure the associated gpio_s as outputs. set the gpxout bits low to configure the associated gpio_s as inputs. for example, for uart1: gp0out configures gpio4, gp1out configures gpio5, gp2out configures gpio6 and gp3out configures gpio7. address: 0x17 mode: r/w bit 7 6 5 4 3 2 1 0 name bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 reset 0 0 0 0 0 0 0 0 address: 0x18 mode: r/w bit 7 6 5 4 3 2 1 0 name gp3od gp2od gp1od gp0od gp3out gp2out gp1out gp0out reset 0 0 0 0 0 0 0 0 max3109
48 _____________________________________________________________________________________ dual serial uart with 128-word fifos gpio data register (gpiodata) each uart has four individually assigned gpio outputs as follows: uart0: gpio0Cgpio3, uart1: gpio4Cgpio7. bits 7C4: gpixdat the gpixdat bits reflect the input logic on the associated gpio_s. for example, for uart1: gp0dat configures gpio4, gp1dat configures gpio5, gp2dat configures gpio6 and gp3dat configures gpio7. when configured as inputs in gpxout, the gpio_s are high-impedance inputs with weak pulldown resistors, regardless of the state of gpxod. bits 3C0: gpoxdat the gpoxdat bits allow programming of the logic state of the gpio_s when configured as outputs in gpioconfg [3:0]. for open-drain operation, pullup resistors are needed on the gpios. for example, for uart1: gp0dat configures gpio4, gp1dat configures gpio5, gp2dat configures gpio6 and gp3dat configures gpio7. address: 0x19 mode: r/w bit 7 6 5 4 3 2 1 0 name gpi3dat gpi2dat gpi1dat gpi0dat gpo3dat gpo2dat gpo1dat gpo0dat reset 0 0 0 0 0 0 0 0 max3109
______________________________________________________________________________________ 49 dual serial uart with 128-word fifos table 4. pllfactorx selection guide figure 17. pll signal path pll configuration register (pllconfig) bits 7C6: pllfactorx the pllfactorx bits allow programming the pll multiplication factor. the input and output frequencies of the pll must be limited to the ranges shown in table 4. enable the pll in clksource [2]. bits 5C0: predivx the predivx bits allow programming of the divisor in the plls predivider. the divisor must be chosen such that the output frequency of the predivider, which is the plls input frequency, is limited to the ranges shown in table 4. the pll input frequency is calculated as: f pllin = f clk /prediv where f clk is the input frequency of the crystal oscillator or external clock source (figure 17), and prediv is an integer in the range of 1 to 63. predivider f clk pll f pllin f ref fractional baud-rate generator address: 0x1a mode: r/w bit 7 6 5 4 3 2 1 0 name pllfactor1 pllfactor0 prediv5 prediv4 prediv3 prediv2 prediv1 prediv0 reset 0 0 0 0 0 0 0 1 pllfactor1 pllfactor0 multiplication factor f pllin f ref min max min max 0 0 6 500khz 800khz 3mhz 4.8mhz 0 1 48 850khz 1.2mhz 40.8mhz 56mhz 1 0 96 425khz 1mhz 40.8mhz 96mhz 1 1 144 390khz 667khz 56mhz 96mhz max3109
50 _____________________________________________________________________________________ dual serial uart with 128-word fifos baud-rate generator configuration register (brgconfig) bits 7 and 6: no function bit 5: 4xmode set the 4xmode bit high to quadruple the regular (16x sampling) baud rate. set the 2xmode bit low when 4xmode is enabled. see the 2x and 4x rate modes section for more information. bit 4: 2xmode set the 2xmode bit high to double the regular (16x sampling) baud rate. set the 4xmode bit low when 2xmode is enabled. see the 2x and 4x rate modes section for more information. bits 3C0: fractx the fractx bits are the fractional portion of the baud-rate generator divisor. set fractx to 0000b if not used. see the fractional baud-rate generator section for calculations of how to set this value to select the baud rate. baud-rate generator lsb divisor register (divlsb) divlsb and divmsb define the baud-rate generator integer divisor. the minimum value for divlsb is 1. see the fractional baud-rate generator section for more information. bits 7C0: divx the divx bits are the eight lsbs of the integer divisor portion (div) of the baud-rate generator. address: 0x1b mode: r/w bit 7 6 5 4 3 2 1 0 name 4xmode 2xmode fract3 fract2 fract1 fract0 reset 0 0 0 0 0 0 0 0 address: 0x1c mode: r/w bit 7 6 5 4 3 2 1 0 name div7 div6 div5 div4 div3 div2 div1 div0 reset 0 0 0 0 0 0 0 1 max3109
______________________________________________________________________________________ 51 dual serial uart with 128-word fifos baud-rate generator msb divisor register (divmsb) divlsb and divmsb define the baud-rate generator integer divisor. the minimum value for divlsb is 1. see the fractional baud-rate generator section for more information. bits 7C0: divx the divx bits are the eight msbs of the integer divisor portion (div) of the baud-rate generator. clock source register (clksource) bit 7: clktorts set the clktorts bit high to route the baud-rate generator (16x baud rate) output clock to rts_ . the rts_ clock fre - quency is a factor of 16x, 8x, or 4x of the baud rate in 1x, 2x, and 4x rate modes, respectively. bits 6, 5, 4, and 0: no function bit 3: pllbypass set the pllbypass bit high to bypass the internal pll and predivider. bit 2: pllen set the pllen bit high to enable the internal pll. set pllen low to disable the internal pll. bit 1: crystalen set the crystalen bit high to enable the crystal oscillator. when using an external clock source at xin, set crystalen low. address: 0x1e mode: r/w bit 7 6 5 4 3 2 1 0 name clktorts pllbypass pllen crystalen reset 0 0 0 1 1 0 0 0 address: 0x1d mode: r/w bit 7 6 5 4 3 2 1 0 name div15 div14 div13 div12 div11 div10 div9 div8 reset 0 0 0 0 0 0 0 0 max3109
52 _____________________________________________________________________________________ dual serial uart with 128-word fifos global irq register (globalirq) bit 7C2: no function bits 1-0: irqx the max3109 has a single irq output. the globalirq register bits report which of the uarts have an interrupt pend - ing, as enabled in the isrinten registers. the globalirq register can be read in two ways: either by reading register 0x1f of any of the two uarts or by sam - pling the two bits sent to the master on miso during the command byte of a read cycle (full-duplex spi) (see the fast read cycle section for more information). the irqx bits are set high when the associated uarts have an irq interrupt pending. the irqx bits are cleared when the associated uart interrupt is cleared. uart interrupts are cleared by reading the uart isr register. address: 0x1f mode: r bit 7 6 5 4 3 2 1 0 name irq1 irq0 reset 0 0 0 0 0 0 1 1 max3109
______________________________________________________________________________________ 53 dual serial uart with 128-word fifos global command register (globlcomnd) bits 7C0: glbcomx the globlcomnd register is the only global write register in the max3109. every byte written to globlcomnd is sent simultaneously to both uarts. every byte sent by the spi/i 2 c master to register 0x1f is interpreted as a global com - mand by both internal uarts, regardless of which uart it was written to. the max3109 logic supports the following commands (table 5): ? global tx synchronization ? extended addressing space enable (to enable access to registers beyond address 0x1f) ? extended addressing space disable (to disable access to registers beyond address 0x1f) the last two commands (0xce/0xcd) enable or disable access to registers in the extended space of the register map when the max3109 operates in spi mode. the spi command byte has only 5 bits to address a given register so that the registers beyond 0x1f could not be addressed using the standard access method. in i 2 c mode, there is no need to explicitly enable and disable the extended register map access as i 2 c allows up to 7 bits for register addressing. to extend the addressing capability of the spi command byte, send a 0xce to location 0x1f. the internal spi address in extended access mode is generated as 0010 a3a2a1a0, where a3a2a1a0 is the least significant nibble of the com - mand byte. bit a4 of the command byte is disregarded when the extended space of the register map is enabled and only the least significant nibble is used for addressing purposes (table 6). the u bit of the command byte maintains its meaning in the extended mode. see the spi interface section for more information. to return to standard addressing mode, the spi master sends the 0xcd command to register 0x1f. in this case, the internal spi address will be generated as follows (default): 000a4 a3a2a1a0. table 5. globlcomnd command descriptions table 6. extended mode addressing (spi only) address: 0x1f mode: w bit 7 6 5 4 3 2 1 0 name glbcom7 glbcom6 glbcom5 glbcom4 glbcom3 glbcom2 glbcom1 glbcom0 globlcomndx command description 0xe0 tx command 0 0xe1 tx command 1 0xe2 tx command 2 0xe3 tx command 3 0xe4 tx command 4 0xe5 tx command 5 0xe6 tx command 6 0xe7 tx command 7 0xe8 tx command 8 0xe9 tx command 9 0xea tx command 10 0xeb tx command 11 0xec tx command 12 0xed tx command 13 0xee tx command 14 0xef tx command 15 0xce enable extended register map access 0xcd disable extended register map access register spi mode address i 2 c mode address txsynch 0x00 0x20 synchdelay1 0x01 0x21 synchdelay2 0x02 0x22 timer1 0x03 0x23 timer2 0x04 0x24 revid 0x05 0x25 max3109
54 _____________________________________________________________________________________ dual serial uart with 128-word fifos transmitter synchronization register (txsynch) the txsynch register is used to configure transmitter synchronization with a global spi or i 2 c command. one of 16 trigger commands (table 5) can be selected to be the synchronization trigger source individually for each uart. this allows simultaneous start of transmission of multiple uarts that are associated with the same global trigger command. the synchronized uarts can be on either a single max3109 or multiple devices if they are controlled by a common spi interface. the uarts start transmission when a global trigger command is received. start of transmission is considered to be the falling edge of the start bit at the tx_ output. a delay can optionally be programmed through the synchdelay1 and synchdelay2 registers. tx synchronization is managed through software by transmitting the broadcast trigger tx command (table 5) to the max3109 through the spi or i 2 c interface. to selectively synchronize ports that are on the same max3109 (intrachip synchronization) or on different max3109 (interchip synchronization) devices, up to 16 trigger tx commands have been defined (see the global command register (globlcomnd) section for more information) . bit 7: clktogpio the clktogpio bit is used to provide a buffered replica of the uarts system clock (i.e., the fractional baud-rate gen - erator input) to a gpio. uart0s clock is routed to gpio0 and uart1s clock is routed to gpio4. bit 6: txautodis set the txautodis bit high to enable automatic transmitter disabling. when txautodis is set high, the transmitter is automatically disabled when all data in the txfifo has been transmitted. after the transmitter is disabled, the txfifo can then be filled with data that will be transmitted when its assigned trigger command is received, as defined by the trigselx bits. bit 5: trigdelay set the trigdelay bit high to enable delayed start of transmission when a trigger command is received. the uart starts transmitting data following a delay programmed in synchdelay1 and synchdelay2 after receiving the assigned trigger command. bit 4: synchen set the synchen bit high to enable software tx synchronization mode. if synchen is set high, the uart starts transmit - ting data when the assigned trigger command is received and the txfifo contains data. setting synchen high forces the mode1 [1]: txdisabl bit high and thereby disables the uarts transmitter. this prevents the transmitter from send - ing data as soon as the txfifo is loaded. once the txfifo has been loaded, the uart starts transmitting data only upon receiving the assigned trigger command. set the synchen bit low to disable transmitter synchronization for that uart. if synchen is set low, that uarts trans - mitter does not start transmission through any trigger command. bits 3C0: trigselx the trigselx bits assign the trigger command for that uarts transmitter synchronization when synchen is set high. for example, set txsynch [3:0] to 0x08 for the uart to be triggered by tx command 8 (0xe8, table 5). address: 0x20 mode: r/w bit 7 6 5 4 3 2 1 0 name clktogpio txautodis trigdelay synchen trigsel3 trigsel2 trigsel1 trigsel0 reset 0 0 0 0 0 0 0 0 max3109
______________________________________________________________________________________ 55 dual serial uart with 128-word fifos synchronization delay register 1 (synchdelay1) the synchdelay1 and synchdelay2 register contents define the time delay between when the uart receives an assigned transmitter trigger command and when the uart begins transmission. bits 7C0: sdelayx the sdelayx bits are the 8 lsbs of the delay between when the uart receives an assigned transmitter trigger com - mand and when the uart begins transmission. the delay is expressed in number of uart bit intervals (1/baudrate). the maximum delay is 65,535 bit intervals. for example, given a baud rate of 230.4kbps, the bit time is 4.34 f s, so the maximum delay is 284ms. synchronization delay register 2 (synchdelay2) the synchdelay1 and synchdelay2 register contents define the time delay between when the uart receives an assigned transmitter trigger command and when the uart begins transmission. bits 7C0: sdelayx the sdelayx bits are the 8 msbs of the delay between when the uart receives an assigned transmitter trigger com - mand and when the uart begins transmission. the delay is expressed in number of uart bit intervals (1/baudrate). the maximum delay is 65,535 bit intervals. for example, given a baud rate of 230.4kbps, the bit time is 4.34 f s, so the maximum delay is 284ms. address: 0x21 mode: r/w bit 7 6 5 4 3 2 1 0 name sdelay7 sdelay6 sdelay5 sdelay4 sdelay3 sdelay2 sdelay1 sdelay0 reset 0 0 0 0 0 0 0 0 address: 0x22 mode: r/w bit 7 6 5 4 3 2 1 0 name sdelay15 sdelay14 sdelay13 sdelay12 sdelay11 sdelay10 sdelay9 sdelay8 reset 0 0 0 0 0 0 0 0 max3109
56 _____________________________________________________________________________________ dual serial uart with 128-word fifos timer register 1 (timer1) the timer1 and timer2 register contents can be used to generate a low-frequency clock signal on a gpio_ output. the low-frequency clock is a divided replica of the fractional baud-rate generator output. if timer1 and timer2 are both 0x00, the low-frequency clock is off. bits 7C0: timerx the timer1 [7:0] bits are the 8 lsbs of the 15-bit timer divisor. see the timer2 register description. timer register 2 (timer2) the timer1 and timer2 register contents can be used to generate a low-frequency clock signal on a gpio_ output. the low-frequency clock is a divided replica of the fractional baud-rate generator output. if timer1 and timer2 are both 0x00, the low-frequency clock is off. bit 7: tmrtogpio set the tmrtogpio bit high to enable clock generation at a gpio output. the clock signal is routed to gpio1 for uart0 and gpio5 for uart1. the output clock has a 50% duty cycle. bits 6C0: timerx the timer2 [6:0] bits are the 7 msbs of the 15-bit timer divisor. the clock frequency is calculated using the following formula: f timer_clk = uartclk/(1024 x timerx) where uartclk is the fractional baud-rate generator output (i.e., 16 x baud rate). revision identification register (revid) bits 7C0: bitx the revid register indicates the revision number of the max3109 silicon starting with 0xc0. this can be used during software development as a known reference. address: 0x24 mode: r/w bit 7 6 5 4 3 2 1 0 name tmrtogpio timer14 timer13 timer12 timer11 timer10 timer9 timer8 reset 0 0 0 0 0 0 0 0 address: 0x25 mode: r bit 7 6 5 4 3 2 1 0 name bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 reset 1 1 0 0 0 0 0 1 address: 0x23 mode: r/w bit 7 6 5 4 3 2 1 0 name timer7 timer6 timer5 timer4 timer3 timer2 timer1 timer0 reset 0 0 0 0 0 0 0 0 max3109
______________________________________________________________________________________ 57 dual serial uart with 128-word fifos serial controller interface the max3109 can be controlled through i 2 c or spi as defined by the logic on spi/ i2c . see the pin description for further details. spi interface the spi supports both single-cycle and burst read/write access. the spi master must generate clock and data signals in spi mode0 (i.e., with clock polarity cpol = 0 and clock phase cpha = 0). each of the two uarts is addressed using 1 bit (u) in the command byte (table 7). to access the registers with addresses 0x20 or higher in spi mode, enable extended register map access. see the globlcomnd register description for more information. spi single-cycle access before a specific uart has been addressed, both uarts could attempt to drive miso. to avoid this con - tention, the miso line is held in high impedance during a write cycle (figure 18). during a read cycle, miso is high impedance for the first four clock cycles of the command byte. once the spi address has been properly decoded, the addressed spi drives the miso line (figure 19). figure 18. spi write cycle figure 19. spi ready cycle table 7. spi command byte configuration ax = register address. high-z ax = register address dx = 8-bit register contents cs sclk mosi miso w0 u a4 a3 a2 a1 a0 d7 d6 d5 d4 d3 d2 d1 d0 high-z ax = register address dx = 8-bit register contents sclk mosi miso r 0 u a4 a3 a2 a1 a0 cs 00 irq1 irq0 d7 d6 d5 d4 d3 d2 d1 d0 spi command byte bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 w/ r 0 u a4 a3 a2 a1 a0 max3109
58 _____________________________________________________________________________________ dual serial uart with 128-word fifos spi burst access burst access allows writing and reading multiple data bytes in one block by defining only the initial register address in the spi command byte. multiple characters can be loaded into the txfifo by using the thr (0x00) as the initial burst write address. similarly, multiple characters can be read out of the rxfifo by using the rhr (0x00) as the spis burst read address. if the spi burst address is different from 0x00, the max3109 auto - matically increments the register address after each spi data byte. efficient programming of multiple consecutive registers is thus possible. the chip-select input, cs /a0, must be held low during the whole cycle. the sclk/scl clock continues clocking throughout the burst access cycle. the burst cycle ends when the spi master pulls cs /a0 high. for example, writing 128 bytes into the txfifo can be achieved by a burst write access using the following sequence: 1) pull cs /a0 low. 2) send spi write command to address 0x00. 3) send 128 bytes. 4) release cs /a0. this takes a total of (1 + 128) x 8 clock cycles. fast read cycle the two uart interrupts on the max3109 share the single irq output. when operating in interrupt-based mode, the microcontroller needs to locate the source of the interrupt (i.e., which of the uarts generated the interrupt) and clear the interrupt. in order to locate the source of an interrupt more quickly, the max3109 implements the spi fast read cycle. this means that the microcontroller can determine which uart is the source of the interrupt (uart0 or uart1) using only 8 clock cycles (figure 20). the u bit is ignored during the fast read cycle. i 2 c interface the max3109 contains an i 2 c-compatible interface for data communication with a host processor (scl and sda). the interface supports a clock frequency of up to 1mhz. scl and sda require pullup resistors that are connected to a positive supply. start, stop, and repeated start conditions when writing to the max3109 using i 2 c, the master sends a start condition (s) followed by the max3109 i 2 c address. after the address, the master sends the register address of the register that is to be pro - grammed. the master then ends communication by issuing a stop condition (p) to relinquish control of the figure 20. spi fast read cycle mosi ax = register address sclk cs miso 0 high-z r u a4 a3 a2 a1 a0 00 irq1 irq0 max3109
______________________________________________________________________________________ 59 dual serial uart with 128-word fifos bus, or a repeated start condition (sr) to communi - cate to another i 2 c slave. see figure 21. slave address the max3109 includes a configurable 7-bit i 2 c slave address, allowing up to 16 max3109 devices to share the same i 2 c bus. the address is defined by connect - ing the mosi/a1 and cs /a0 inputs to dgnd, v l , scl, or sda (table 5). set the r/ w bit high to configure the max3109 to read mode. set the r/ w bit low to config - ure the max3109 to write mode. the address is the first byte of information sent to the max3109 after the start condition. bit transfer one data bit is transferred on the rising edge of each scl clock cycle. the data on sda must remain stable during the high period of the scl clock pulse. changes in sda while scl is high and stable are considered control signals (see the start, stop, and repeated start conditions section). both sda and scl remain high when the bus is not active. figure 21. i 2 c start, stop, and repeated start conditions table 8. i 2 c address map scl sda ss rp mosi/a1 cs /a0 uart0 uart1 write read write read dgnd dgnd 0xd8 0xd9 0xb8 0xb9 dgnd v l 0xc2 0xc3 0xa2 0xa3 dgnd scl 0xc4 0xc5 0xa4 0xa5 dgnd sda 0xc6 0xc7 0xa6 0xa7 v l dgnd 0xc8 0xc9 0xa8 0xa9 v l v l 0xca 0xcb 0xaa 0xab v l scl 0xcc 0xcd 0xac 0xad v l sda 0xce 0xcf 0xae 0xaf scl dgnd 0xd0 0xd1 0xb0 0xb1 scl v l 0xd2 0xd3 0xb2 0xb3 scl scl 0xd4 0xd5 0xb4 0xb5 scl sda 0xd6 0xd7 0xb6 0xb7 sda dgnd 0xc0 0xc1 0xa0 0xa1 sda v l 0xda 0xdb 0xba 0xbb sda scl 0xdc 0xdd 0xbc 0xbd sda sda 0xde 0xdf 0xbe 0xbf max3109
60 _____________________________________________________________________________________ dual serial uart with 128-word fifos single-byte write in this operation, the master sends an address and two data bytes to the slave device (figure 22). the following procedure describes the single-byte write operation: 1) the master sends a start condition. 2) the master sends the 7-bit slave address plus a write bit (low). 3) the addressed slave asserts an ack on the data line. 4) the master sends the 8-bit register address. 5) the slave asserts an ack on the data line only if the address is valid (nack if not). 6) the master sends 8 data bits. 7) the slave asserts an ack on the data line. 8) the master generates a stop condition. burst write in this operation, the master sends an address and mul - tiple data bytes to the slave device (figure 23). the slave device automatically increments the register address after each data byte is sent, unless the register being accessed is 0x00, in which case the register address remains the same. the following procedure describes the burst write operation: 1) the master sends a start condition. 2) the master sends the 7-bit slave address plus a write bit (low). 3) the addressed slave asserts an ack on the data line. 4) the master sends the 8-bit register address. 5) the slave asserts an ack on the data line only if the address is valid (nack if not). 6) the master sends 8 data bits. 7) the slave asserts an ack on the data line. 8) repeat 6 and 7 n-1 times. 9) the master generates a stop condition. figure 22. write byte sequence figure 23. burst write sequence s p device slave address - w a 8 data bits from master to stave write single byte from slave to master a register address a s device slave address - w a 8 data bits - 1 burst write a register address a 8 data bits - n a 8 data bits - 2 a from master to stave from slave to master p max3109
______________________________________________________________________________________ 61 dual serial uart with 128-word fifos single-byte read in this operation, the master sends an address plus two data bytes and receives one data byte from the slave device (figure 24). the following procedure describes the single-byte read operation: 1) the master sends a start condition. 2) the master sends the 7-bit slave address plus a write bit (low). 3) the addressed slave asserts an ack on the data line. 4) the master sends the 8-bit register address. 5) the active slave asserts an ack on the data line only if the address is valid (nack if not). 6) the master sends a repeated start condition. 7) the master sends the 7-bit slave address plus a read bit (high). 8) the addressed slave asserts an ack on the data line. 9) the slave sends 8 data bits. 10) the master asserts a nack on the data line. 11) the master generates a stop condition. burst read in this operation, the master sends an address plus two data bytes and receives multiple data bytes from the slave device (figure 25). the following procedure describes the burst byte read operation: 1) the master sends a start condition. 2) the master sends the 7-bit slave address plus a write bit (low). 3) the addressed slave asserts an ack on the data line. 4) the master sends the 8-bit register address. 5) the slave asserts an ack on the data line only if the address is valid (nack if not). 6) the master sends a repeated start condition. 7) the master sends the 7-bit slave address plus a read bit (high). figure 24. read byte sequence figure 25. burst read sequence s sr device slave address - w a device slave address - r read single byte a register address a 8 data bits na from master to stave from slave to master p s sr device slave address - w a device slave address - r burst read a register address a 8 data bits - 1a a 8 data bits - 3 8 data bits - 2a 8 data bits - nn a from master to stave from slave to master p max3109
62 _____________________________________________________________________________________ dual serial uart with 128-word fifos 8) the slave asserts an ack on the data line. 9) the slave sends 8 data bits. 10) the master asserts an ack on the data line. 11) repeat 9 and 10 n-2 times. 12) the slave sends the last 8 data bits. 13) the master asserts a nack on the data line. 14) the master generates a stop condition. acknowledge bits data transfers are acknowledged with an acknowledge bit (ack) or a not-acknowledge bit (nack). both the master and the max3109 generate ack bits. to generate an ack, pull sda low before the rising edge of the ninth clock pulse and hold it low during the high period of the ninth clock pulse (figure 26). to generate a nack, leave sda high before the rising edge of the ninth clock pulse and leave it high for the duration of the ninth clock pulse. monitoring for nack bits allows for detection of unsuc - cessful data transfers. applications information startup and initialization the max3109 can be initialized following power-up, a hardware reset, or a software reset as shown in figure 27. to verify that the max3109 is ready for opera - tion after a power-up or reset. repeatedly read a known register until the expected contents are returned. the max3109 is ready for opera - tion after approximately 200 f s. figure 26. acknowledge figure 27. startup and initialization flowchart not-acknowledge acknowledge 12 89 sda scl s power-up/ rst input pulled high is divlsb read successfully? y n configure clocking configure modes configure fifo control configure flow control configure gpios start communication enable interrupts max3109
______________________________________________________________________________________ 63 dual serial uart with 128-word fifos low-power operation to reduce the power consumption during normal opera - tion, the following techniques can be adopted: ? do not use the internal pll. this saves the most power of the options listed here. disable and bypass the pll. with the pll enabled, the current to the v cc supply is in the range of a few ma (depending on clock frequency and multiplication factor), while it drops to below 1ma if disabled. ? use an external clock source. the lowest power clocking mode is when an external clock signal is used. this drops the power consumption to about half that of an external crystal. ? keep the internal clock rates as low as possible. ? use a low voltage on the v cc supply. ? use an external 1.8v supply. this saves the power dissipated by the internal 1.8v linear regulator for the 1.8v core supply. connect an external 1.8v supply to v 18 and disable the internal regulator by connecting ldoen to dgnd. interrupts and polling monitor the max3109 by polling the isr register or by monitoring the irq output. in polled mode, the irq physical interrupt output is not used and the host control - ler polls the isr register at frequent intervals to establish the state of the max3109. alternatively, the physical irq interrupt can be used to interrupt the host controller after specified events, mak - ing polling unnecessary. the irq output is an open-drain output that requires a pullup resistor to v l . logic-level translation the max3109 can be directly connected to transceivers and controllers that have different supply voltages. the v l input defines the logic voltage levels of the controller inter - face, while the v ext voltage defines the logic of the trans - ceiver interface. this ensures flexibility when selecting a controller and transceiver. figure 28 shows an example of a configuration where the controller, transceiver, and the max3109 are powered by three different supplies. figure 28. logic-level translation max3109 tx_ rx_ rts_ agnd dgnd v l v cc v ext rst irq spi/i 2 c max14840e transceiver v cc di de ro v dd 2.5v 1.8v 3.3v microcontroller max3109
64 _____________________________________________________________________________________ dual serial uart with 128-word fifos power-supply sequencing the devices power supplies can be turned on in any order. each supply can be present over the entire speci - fied range regardless of the presence or level of the others. ensure the presence of the interface supplies v l and v ext before sending input signals to the controller and transceiver interfaces. connector sharing the tx_ and rts_ outputs can be programmed to be high impedance. this feature is used in cases where the max3109 shares a common connector with other com - munications devices. set the output of the max3109 to high impedance when the other communication devices are active. set the mode1 [2]: txhiz bit high to set tx_ to a high-impedance state. set the mode1 [3]: rtshiz bit high to set rts_ to a high-impedance state. figure 29 shows an example of connector sharing with a usb transceiver. rs-232 5x3 application the four gpios can be used to implement the other flow control signals defined in itu v.24. figure 30 shows how the gpios create the dsr, dtr, dcd, and ri signals found on some rs-232/v.28 interfaces. set the flowctrl [1:0] bits high to enable automatic hard - ware rts_ / cts_ flow control. figure 29. connector sharing with a usb transceiver figure 30. rs-232 application max3109 tx_ rx_ max13481e d+ d- oe tx/d+ rx/d- shared connector max3109 tx0 rx0 tx rx spi/i 2 c max3245 t1in r1out microcontroller rst ldoen irq rts0 cts0 rts cts t2in r2out gpio0 gpio1 dtr dsr t3in r3out gpio2 gpio3 dcd ri r4out r5out max3109
______________________________________________________________________________________ 65 dual serial uart with 128-word fifos figure 31. rs-485 half-duplex application typical application circuit figure 31 shows the max3109 being used in a half- duplex rs-485 application. the microcontroller, the rs-485 transceiver, and the max3109 are powered by a single 3.3v supply. spi is used as the controllers com - munication interface. the microcontroller provides an external clock source to clock the uart. the max14840 receiver is always enabled, so echoing occurs. enable auto echo suppression in the max3109 by setting the mode2 [7]: echosuprs bit high. set the mode1 [4]: transcvctrl bit high to enable auto transceiver direction control in order to automatically control the de input of the transceiver. chip information process: bicmos package information for the latest package outline information and land patterns (footprints), go to www.maxim-ic.com/packages . note that a +, #, or - in the package code indicates rohs status only. package drawings may show a different suffix character, but the drawing pertains to the package regardless of rohs status. max14840e a1 b1 di ro re de max3109 tx0 rx0 agnd dgnd v 18 v cc v ext v l irq spi/i2c ldoen xout rst xin spi 3.3v microcontroller rts0 max14840e a2 b2 di ro re de tx1 rx1 rts1 10k 0.1 f 0.1 f package type package code outline no. land pattern no. 32 tqfn-ep t3255+1 21-0180 90-0012 max3109
maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a maxim product. no circuit patent licenses are implied. maxim reserves the right to change the circuitry and specifications without notice at any time. 66 maxim integrated products, 120 san gabriel drive, sunnyvale, ca 94086 408-737-7600 ? 2012 maxim integrated products maxim is a registered trademark of maxim integrated products, inc. dual serial uart with 128-word fifos revision history revision number revision date description pages changed 0 3/11 initial release 1 5/12 corrected for improved shutdown current mode and specifications, including low- power shutdown mode configurations 1, 7, 14, 15, 27, 38, 62 max3109

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